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Is the cost reduction associated with IC scaling over?
Zvi Or-Bach, MonolithIC 3D Inc.
7/16/2012 12:20 PM EDT
The last 50 years of the semiconductor industry have been all about the manifestation of Moore's Law with regard to the dimensional scaling of Integrated Circuits (ICs). As consumers of electronic devices, we all love to see better products at a lower cost with each and every new product cycle. But now storm clouds are forming, as was recently publicly expressed in the article Nvidia deeply unhappy with TSMC, claims 20nm essentially worthless (click here to see the original article).
Clearly, dimensional scaling is no longer associated with lower average cost per transistor. The chart below, published by IBS about a year ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.
The following Nvidia chart provides the first order explanation. The cost reduction of dimensional scaling results from doubling the number of transistors per wafer. But if the wafer cost of the new technology node increases by too much, then it neutralizes the original cost reduction. The Nvidia chart shows the wafer cost of recent nodes over time.
In the past (...80nm, 55nm, 40nm), the incremental wafer cost increases were small, and rapid depreciation of those costs resulted in almost constant average wafer price. Recent nodes (28nm, 20nm, 14nm...), however, signal a new reality.
The following (somewhat busy) slide from IBM summarizes things clearly saying: "Net: neither per wafer nor per gate showing historical cost reduction trends"
The number one driver when it comes to increasing wafer costs is the increase in the equipment cost required for processing the next technology node. The following chart presents the increase in costs of capital, process R&D, and design:
The sharp increase of costs associated with scaling is a new phenomenon. There were always costs to move from one node to the next, but they were about constant or incrementally small.
The following slide presents the innovations that enable dimensional scaling. Clearly, for many nodes we were able to use the same lithography tools. But once dimensional scaling reached the limit of light wavelength the lithography tool became critical and dominant. About for every node the lithography became a major challenge that required newer equipment and substantial process R&D. Moreover, in the recent lithography nodes the transistor itself required significant innovation at every node (high-k, Metal Gate, Strain, SiGe, Tri-gate,...) and it is clear that future scaled nodes will require even more of those innovations and their associated costs.
An important part of these costs is the escalating cost of the capital equipment for the next node fabrication lines. The following figure present the cost dynamic for the lithography equipment. Note the logarithmic scale of the cost axis.
Lithography tools grew from less than 10% of wafer fab equipment (WFE) spending to over 25% and accordingly lithography now represents about 50 % of the wafer cost.
An interesting implication of growing domination of lithography in semiconductor processing is the fact that the ASML, which is the lead vendor of lithography tool, recently passed Applied Material's (the leader of all other tools) market cap. Following is the chart of the stock price of ASML (in red) vs. Applied Material (AMAT).
The clear conclusion of all of this is that future dimensional scaling is not about to change these trends. Accordingly, as stated in the IBM slide above: "Net: neither per wafer nor per gate showing historical cost reduction trends." Unless ...
…unless we change the way we do scaling (remember Einstein's famous quote). Moore's Law is about doubling the number of transistors in a semiconductor device. At the time Moore first postulated this, dimensional scaling was one of the three trends he described that would enable the observed and predicted exponential increase of device integration. It would seem that it is about time to look on another one of those – increasing the die size. If we do this by using the third dimension – monolithic 3D-IC – we can achieve both higher integration and cost reduction!
It is not that we should stop scaling down – It's just that if we augment this with "scaling up" (moving to the third dimension), we can introduce the required changes that can achieve the continuation of the cost reduction trend. Clearly, almost all of the increases of wafer costs are related to the pace of dimensional scaling. If those costs could be spread over four years instead of two then the increase in wafer cost would be only about half of what it is now.
It might not be so clear, however, as to why monolithic 3D should reduce wafer cost. Shouldn't the cost of the double die size spread over two layers be at least double…?
In fact, the use of monolithic 3D IC technology would reduce wafer cost because of the following elements:
Let's consider at each of these points in a little more detail…
Reduced Die Size
Dimensional scaling has always been associated with an increase of wire resistivity and capacitance. The industry has spent a huge effort to overcome these by first replacing the conducting material with copper and then changing the isolation material to low-K dielectrics. But the interconnect problem is still growing as demonstrated in the following chart.
Every node of dimensional scaling is associated with larger cells, output drivers, and more buffers and repeaters. Monolithic 3D enables one to fold the circuit such that each additional layer is only around 1µm thick, with very rich vertical connectivity between strata. The following IBM/MIT slide illustrates the effectiveness of such folding.
Further, the reduced silicon area generates an additional reduction of buffers and the average transistor size. MonolithIC 3D Inc. released an open-source top level simulator IntSim v2.0 to simulate a given design's expected size and power based on process parameters and the number of strata (more than 300 copies have been downloaded so far).
Using this simulator, as illustrated in the following table, we can see that a design that uses 50 mm2 with average size gate size of 6 W/L, will now need an average gate size of 3 W/L and accordingly only 24 mm2 if folded into two strata (the footprint will be therefore just 12 mm2).
These results are in-line with many other monolithic 3D research results.
Depreciation
The semiconductor industry is very capital intensive, and a very significant part of the wafer cost is associated with the cost of capital. Since every two years we have been scaling to a new node, then the wafer cost needs to support this rapid loss of capital value. Achieving the next level of device functionality using the same generation of tools allows for a far better utilization of the investment capital. In addition the learning curve of yield and manufacturing efficiency contributes further to the end-product cost reduction. The following chart portion demonstrates this well known trend.
Heterogeneous Integration
Let's start by quoting Mark Bohr, the person in charge of Intel's process development:
The most important market for semiconductor products is smart mobility. For this market the SoC device needs to integrate many functions. In most cases the pure high-performance logic would be about 25% of the die area, 50% would be memories and the rest would be analog functions such as I/O. In 2D they all need to be processed together and bear the same manufacturing costs. In a monolithic 3D-IC stack using heterogeneous integration each stratum is processed in an optimized flow, allowing for a significant cost reduction. The following illustration suggests the use of only two strata to build a device that in 2D would have a size of 196 mm2. By having one stratum for logic and one for memory, and by using DRAM instead of SRAM, the device could be reduced to 98 mm2 with footprint of 49 mm2. The device cost would be further reduced by the memory using only 3 or 4 metal layers.
Multiple Layers Processed Together
Using the right architecture, multiple transistor layers could be processed together with a huge reduction in cost per layer. This could be applied to many different types of regular devices. The following image illustrates the concept with respect to a floating-body DRAM:
MonolithIC 3D Inc's website presents more details for the DRAM flow, and also related flows for RRAM and NAND Flash memories.
In short, we do have a path to continue the semiconductor industry drive for better products and with lower costs, but we should continuously apply innovation to do so. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.
About the author
Zvi Or-Bach is the founder of MonolithIC 3D Inc., which was judged Top Embedded Innovator-Silicon by Embedded Computing Design Magazine and Finalist of the "Best of Semicon West 2011" for its monolithic 3D-IC breakthrough. Or-Bach was also a finalist of the EE Times Innovator of the Year Award in 2011 and 2012 for his pioneering work on the monolithic 3D-IC.
Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company's CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB. Under Or-Bach's leadership, eASIC won the prestigious EE Times' 2005 ACE Award for Ultimate Product of the year in the Logic and Programmable Logic category.
Earlier, Or-Bach founded Chip Express in 1989 and served as the company's President and CEO for almost 10 years, bringing the company to $40M revenue and to industry recognition for three consecutive years as a high-tech Fast 50 Company.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
Clearly, dimensional scaling is no longer associated with lower average cost per transistor. The chart below, published by IBS about a year ago, shows the diminishing benefit of cost reduction from dimensional scaling. In fact, the chart indicates that the 20nm node might be associated with higher cost than the previous node.
The following Nvidia chart provides the first order explanation. The cost reduction of dimensional scaling results from doubling the number of transistors per wafer. But if the wafer cost of the new technology node increases by too much, then it neutralizes the original cost reduction. The Nvidia chart shows the wafer cost of recent nodes over time.
In the past (...80nm, 55nm, 40nm), the incremental wafer cost increases were small, and rapid depreciation of those costs resulted in almost constant average wafer price. Recent nodes (28nm, 20nm, 14nm...), however, signal a new reality.
The following (somewhat busy) slide from IBM summarizes things clearly saying: "Net: neither per wafer nor per gate showing historical cost reduction trends"
The number one driver when it comes to increasing wafer costs is the increase in the equipment cost required for processing the next technology node. The following chart presents the increase in costs of capital, process R&D, and design:
The sharp increase of costs associated with scaling is a new phenomenon. There were always costs to move from one node to the next, but they were about constant or incrementally small.
The following slide presents the innovations that enable dimensional scaling. Clearly, for many nodes we were able to use the same lithography tools. But once dimensional scaling reached the limit of light wavelength the lithography tool became critical and dominant. About for every node the lithography became a major challenge that required newer equipment and substantial process R&D. Moreover, in the recent lithography nodes the transistor itself required significant innovation at every node (high-k, Metal Gate, Strain, SiGe, Tri-gate,...) and it is clear that future scaled nodes will require even more of those innovations and their associated costs.
An important part of these costs is the escalating cost of the capital equipment for the next node fabrication lines. The following figure present the cost dynamic for the lithography equipment. Note the logarithmic scale of the cost axis.
Lithography tools grew from less than 10% of wafer fab equipment (WFE) spending to over 25% and accordingly lithography now represents about 50 % of the wafer cost.
An interesting implication of growing domination of lithography in semiconductor processing is the fact that the ASML, which is the lead vendor of lithography tool, recently passed Applied Material's (the leader of all other tools) market cap. Following is the chart of the stock price of ASML (in red) vs. Applied Material (AMAT).
The clear conclusion of all of this is that future dimensional scaling is not about to change these trends. Accordingly, as stated in the IBM slide above: "Net: neither per wafer nor per gate showing historical cost reduction trends." Unless ...
…unless we change the way we do scaling (remember Einstein's famous quote). Moore's Law is about doubling the number of transistors in a semiconductor device. At the time Moore first postulated this, dimensional scaling was one of the three trends he described that would enable the observed and predicted exponential increase of device integration. It would seem that it is about time to look on another one of those – increasing the die size. If we do this by using the third dimension – monolithic 3D-IC – we can achieve both higher integration and cost reduction!
It is not that we should stop scaling down – It's just that if we augment this with "scaling up" (moving to the third dimension), we can introduce the required changes that can achieve the continuation of the cost reduction trend. Clearly, almost all of the increases of wafer costs are related to the pace of dimensional scaling. If those costs could be spread over four years instead of two then the increase in wafer cost would be only about half of what it is now.
It might not be so clear, however, as to why monolithic 3D should reduce wafer cost. Shouldn't the cost of the double die size spread over two layers be at least double…?
In fact, the use of monolithic 3D IC technology would reduce wafer cost because of the following elements:
- Reduced Die Size: It has been shown in many research studies that each folding into 3D has the potential to reduce the total required silicon area by 50% due to the reduced re-buffering and reduced sizing of the buffers.
- Depreciation: Scaling up enables the use of the same fab and process R&D for few additional years with the associated improvement in deprecation costs and improved manufacturing efficiencies and yield.
- Heterogeneous Integration: Scaling up would enable heterogeneous integration. This will open up the third trend of Moore- improved circuit design. As each strata of 3D IC could be processed in a different flow, cost and power could be saved by using a different process flow for logic, memory and I/O.
- Multiple Layers Processed Together: This would be most effective for a memory type circuits. Using the right architecture, multiple transistors layers could be processed simultaneously, resulting in a huge reduction of cost per layer.
Let's consider at each of these points in a little more detail…
Reduced Die Size
Dimensional scaling has always been associated with an increase of wire resistivity and capacitance. The industry has spent a huge effort to overcome these by first replacing the conducting material with copper and then changing the isolation material to low-K dielectrics. But the interconnect problem is still growing as demonstrated in the following chart.
Every node of dimensional scaling is associated with larger cells, output drivers, and more buffers and repeaters. Monolithic 3D enables one to fold the circuit such that each additional layer is only around 1µm thick, with very rich vertical connectivity between strata. The following IBM/MIT slide illustrates the effectiveness of such folding.
Further, the reduced silicon area generates an additional reduction of buffers and the average transistor size. MonolithIC 3D Inc. released an open-source top level simulator IntSim v2.0 to simulate a given design's expected size and power based on process parameters and the number of strata (more than 300 copies have been downloaded so far).
Using this simulator, as illustrated in the following table, we can see that a design that uses 50 mm2 with average size gate size of 6 W/L, will now need an average gate size of 3 W/L and accordingly only 24 mm2 if folded into two strata (the footprint will be therefore just 12 mm2).
These results are in-line with many other monolithic 3D research results.
Depreciation
The semiconductor industry is very capital intensive, and a very significant part of the wafer cost is associated with the cost of capital. Since every two years we have been scaling to a new node, then the wafer cost needs to support this rapid loss of capital value. Achieving the next level of device functionality using the same generation of tools allows for a far better utilization of the investment capital. In addition the learning curve of yield and manufacturing efficiency contributes further to the end-product cost reduction. The following chart portion demonstrates this well known trend.
Heterogeneous Integration
Let's start by quoting Mark Bohr, the person in charge of Intel's process development:
"One important perspective is that chip technology is becoming more heterogeneous. If you go back 10 or 20 years ago, it was homogenous. There was a CMOS transistor, it was the same materials for NMOS and PMOS, maybe different dopant atoms, and that basic CMOS transistor fit the needs of both memory and logic. Going forward we'll see chips and 3D packages that combine more heterogeneous elements, different materials, and maybe transistors with very different structures whether they're for logic or memory or analog. Combining these very different devices onto one chip or into a 3D stack – that's what we'll see. It will be heterogeneous integration"
The most important market for semiconductor products is smart mobility. For this market the SoC device needs to integrate many functions. In most cases the pure high-performance logic would be about 25% of the die area, 50% would be memories and the rest would be analog functions such as I/O. In 2D they all need to be processed together and bear the same manufacturing costs. In a monolithic 3D-IC stack using heterogeneous integration each stratum is processed in an optimized flow, allowing for a significant cost reduction. The following illustration suggests the use of only two strata to build a device that in 2D would have a size of 196 mm2. By having one stratum for logic and one for memory, and by using DRAM instead of SRAM, the device could be reduced to 98 mm2 with footprint of 49 mm2. The device cost would be further reduced by the memory using only 3 or 4 metal layers.
Multiple Layers Processed Together
Using the right architecture, multiple transistor layers could be processed together with a huge reduction in cost per layer. This could be applied to many different types of regular devices. The following image illustrates the concept with respect to a floating-body DRAM:
MonolithIC 3D Inc's website presents more details for the DRAM flow, and also related flows for RRAM and NAND Flash memories.
In short, we do have a path to continue the semiconductor industry drive for better products and with lower costs, but we should continuously apply innovation to do so. Now that monolithic 3D is practical, it is time to augment dimensional scaling with monolithic 3D-IC scaling.
About the author
Zvi Or-Bach is the founder of MonolithIC 3D Inc., which was judged Top Embedded Innovator-Silicon by Embedded Computing Design Magazine and Finalist of the "Best of Semicon West 2011" for its monolithic 3D-IC breakthrough. Or-Bach was also a finalist of the EE Times Innovator of the Year Award in 2011 and 2012 for his pioneering work on the monolithic 3D-IC.Prior to MonolithIC 3D, Or-Bach founded eASIC in 1999 and served as the company's CEO for six years. eASIC was funded by leading investors Vinod Khosla and KPCB. Under Or-Bach's leadership, eASIC won the prestigious EE Times' 2005 ACE Award for Ultimate Product of the year in the Logic and Programmable Logic category.
Earlier, Or-Bach founded Chip Express in 1989 and served as the company's President and CEO for almost 10 years, bringing the company to $40M revenue and to industry recognition for three consecutive years as a high-tech Fast 50 Company.
If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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resistion
7/17/2012 12:33 AM EDT
One reason 20 nm seems so painful is they are still using 0.7 shrink even with double patterning.
It would make more sense to get close to ~0.5 shrink on the layers which really need DP. Almost like skipping a node to make up.
3D tight arrangement is superior to planar except for thermal, which is its fatal weakness.
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Or_Bach
7/17/2012 3:06 AM EDT
Thermal is not a handicap of monolithic 3D but rather an advantage. The shorter lines means much less power for the same function.And the thin layers allow for easy remove of the upper layer heat.
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George Storm
7/17/2012 5:52 AM EDT
Dedicated proponents can be the worst enemies of the case they are promoting. Sometimes the problem is saying sceptics' proper reservations are irrelevant without providing evidence; sometimes it's merely overselling the technology.
Consider the claim for "shorter lines means much less power..." Halving the area per se at best reduces the line length by a factor of sqrt(2), so the power-per-area increases.
There are special cases where 3D will require a similar number of layers to the parent processes, but this should not be confused with a general advantage. So far as I understand, the "thinner layers" applies only to the silicon, which is definitely not an advantage, as the high thermal conductivity of the substrate in practice provides significant spreading of heat. Moreover, the diagrams as presented place the multi-planar (monolithic 3-D) silicon layers between the substrate and the metallisation; if correct, double-sided heat sinking will be no more straightforward for these 3D structires than it would for 2D structures.
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Or_Bach
7/17/2012 12:36 PM EDT
The preamble suggest that this might not be the place for detailed answers (which we do have). So I will just point out that the most important market for electronics these days is the 'smart mobility'. In this market the main concern is reduction of overall power per function. And the power reduction is actually by factor of 2 as we detail in: http://www.monolithic3d.com/2/post/2012/05/the-future-is-the-interconnect-iitc.html.
As for the issue of removal of the generated power we have worked on it with a team at Stanford and recently the work was reported in a paper submitted to IEDM.
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George Storm
7/17/2012 5:04 PM EDT
What your reference compares is 3d-monolithic versus the wire length for stacked dice using TSV. I wouldn't argue with that. Unfortunately you used this to answer a comment that almost certainly related to use of a single larger 2d die. The advantages of somewhat reduced power then follow the law that I described. And I can't find any evidence for 3d-mono having a double-sided heatsink advantage whichcever case you choose. (Of course, if the process characteristics are different for the different 3d mono active layers, the cost advantage is clear.)
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resistion
7/17/2012 9:24 PM EDT
If you have two planes of hot transistors, it's always hot in between, without convectively pumping the heat out.
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DaveWyland
7/19/2012 2:59 PM EDT
As the CTO of IBM once said, "... somewhere between 130 nm and 90 nm, we lost scaling." Until then, a shrink was 2D. Then, we had to start thinning the metal to avoid skyscraper shorts. This means that the relative resistance of the metal goes UP, rather than staying constant as in previous shrinks. Higher metal resistance means relatively lower speed and higher power. So, shrink a chip and it becomes cheaper (in Si area) but slower and hotter. And that is why we have no 4 GHz Pentiums to this day. The 3.5 GHz Pentium 4 in 2004 was as close as it got.
And now the other shoe is falling. We have pulled out all the stops, with copper, halfnium oxide, etc. so we cannot stave off slower and hotter much longer. Maybe graphene (unobtanium?) will somehow save us. Or not.
3D may help - or not, as comments above seem to indicate.
The Singularity may be delayed until further notice.
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Or_Bach
7/19/2012 8:22 PM EDT
Thanks for the support. And in respect to Singularity, we should be able to bring it sooner thank to monolithic 3D as we presented in our blog titled "Monolithic 3D IC Could Increase Circuit Integration by 1,000x": http://www.monolithic3d.com/2/post/2011/12/monolithic-3d-ic-could-increase-circuit-integration-by-1000x.html
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bec
7/19/2012 9:11 PM EDT
As for the TSV study at IITC (Fig. 6 in the linked blog post) the point is that for 5um TSVs, the gain in 3D wirelength shorting over 2D is minimal (90nm 2D at 75um goes to maybe 74um 3D). But for a 0.1um TSV, the wire shortening is quite significant (90nm 2D at 75um goes to 45um 3D).
http://www.monolithic3d.com/2/post/2012/05/the-future-is-the-interconnect-iitc.html
Another way to look at it: The power savings of a factor of 2 does not come just by area savings and the resultant shorter wires with mon 3D (footprint is actually 4X lower), but also by the minimization of the slow metallization scaling 'bandaid' we all have been using for so many scaling generations--the repeaters/buffers. As they get eliminated by the mon3D shorter wires, the transistors become closer and the horizontal wires between them shorter….a positive feedback. Try it out on the MonolithIC3D website: 3D and 2D free simulator.
http://www.monolithic3d.com/simulators.html
As for heat removal from the second layer (‘top’ one farthest away from the heat sink), the heat removal is not dominated by ‘double-sided’ convection, but by intentional conduction (think satellites as an analog, but we have a heat sink advantage they don’t); and if done properly, taking advantage of the mon3D dense vertical connects for thermal as well as electrical conduction, a lot of heat generation from the second layer can be taken to the heat sink. As Zvi mentioned, the paper with Stanford has been submitted.
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