Industry View: LeCroy's CTO on the strategic advantage you might be missing

We caught up with Dave Graef, CTO of LeCroy, to get his take on some of the technical challenges going on in the test market and process changes manufacturers can make to improve their products and speed integration.

Kristin Lewotsky, editor: What's the biggest challenge right now in the high-performance oscilloscope?
Dave Graef: Scopes evolved from viewing tools. Back when they were analog scopes, you could see the waveform and almost make measurements on the grid if you lined it up right. Now, they’re expected to be a fine-measurement instrument. All the considerations in the signal path have gotten much more important. For simply a viewing tool, I could probably get away with 3% distortion, a signal-to-noise ratio of 30 to 35 dB, something like that. But now, all those characteristics have to be much, much better. Even the 8-bit ADC starts to put some limitations on the kinds of things people want to do. We’ve recently started making oscilloscopes with 12-bit ADCs that have better characteristics from the DC accuracy, signal-to-noise, and linearity perspective in order to try to maintain accuracy across the full bandwidth of the instrument.

KL: I assume going to 12 bits increases price and complexity, but it also slows down sampling time, right?
DG: With technology today, we can't sample as fast with 12 bits as we could with 8 bits. For example the basic building block we use in our scope is our 40 gigasample 8-bit ADC. At 12 bits, we're at around 2.5 gigasamples. We'd like to have 12 bits as far up in sample rate as we can, but we can't violate the basic laws of physics. There are technical limitations. That said, technical limitations have a way of getting beaten down over time.

KL: You're known for high-end oscilloscopes. With the Teledyne acquisition, are you likely to broaden beyond that?
DG: We have other products—low-end arbitrary waveform generators, a TDR, and we have a protocol-aware bit-error-rate tester. As the standards go higher and higher in frequency, for example PCI Express Gen 3, part of the specification says that the test equipment has to negotiate with the receiver over a live link what the transmit pre-emphasis should be, so the test equipment needs to understand what is being communicated to it by the receiver at protocol level and make the appropriate changes.

KL: As far as test goes, what do you think designers should do differently?
DG: Thinking about how things should be tested and validated a little bit further upstream really helps. Maybe at the design level try to drive some of the test capabilities built into the chip. There's been talk in the industry about that kind of thing for some time—there’s the digital JTAG that's made its way into virtually everything. There's an analog equivalent of that that never really gained any traction for obvious reasons—it's hard to tap analog devices without screwing them up. I think there are other things that are a little more viable like putting some test [components] on the chip that can aid test equipment in order to get a full picture of what's going on.


KL: What types of test elements would you put on chip?
DG: For many of these high-speed serial links, you can have to look at the eye pattern and make adjustments. Being able to access and use that data as we're making measurements at the physical level with the scope might be an interesting thing to do. As an industry, thinking about [test] a little more holistically—what things are best put on the chip what things are better measured off the chip—thinking about things that way may be very beneficial moving forward. All of these things get solved eventually but it all takes longer than we expect because collectively we’re kind of iterating to find a solution.

I don't know what the answer is—it's hard enough to get a whole bunch of people together within a company to define an architecture. To define an architecture and implement it industry-wide with a few twists to give everyone a competitive advantage, that's a really difficult problem. And yet if we could figure out a way to do that, I think we could move ahead even faster than we are today.

KL: When I talk to the power guys I often hear that they get handed the prototype at the last minute and told, "We need a power supply with better than 1 dB of noise by tomorrow and you’ve got 1 mm² of space and 0.0001% of budget to do it with.” Early design in can make all the difference.
DG: I think the power analogy is a good one because the power supply is the last thing you think of. Actually, we've learned that that's the first thing we have to consider—how are we going to power all of these chips to make sure we don't get crosstalk between channels, because power supply architecture and power distribution architectures are really critical for maintaining high signal-to-noise ratios. In an analog system where you’re trying to maintain extremely good signal, everything matters.

KL: What do you wish your customers knew?
DG: Test can be a very strategic part of your business. I think if people thought of test as a strategic weapon, then they would do things differently earlier in the design cycle. You get what you measure. Thinking about how you’re going to test something makes you think about the things you ought to be thinking about at the design stage. If you're thinking about how you're going to test [the device] in production, it's probably going to test well when you get there. If I don't think about it, it probably won't.

It's like us making these simple statements that we want to move to 12 bits as far up and down the line as possible. That has implications for the entire signal chain, the power distribution, the entire design of the instrument. To make a statement like, "Test is a very strategic weapon for us and here's why" has implications up and down the line. Thinking that way could be very good thing for everyone involved.