What’s happening at OCP-IP

7/26/2012 10:07 AM EDT

Recently, I got to speak with Ian Mackintosh who wanted to bring me up to date with everything that has been happening at OCP recently. So let’s start with who they are and what they do, that way everyone is on the same page. OCP standards for Open Core Protocol and enables intellectual property (IP) blocks to be delivered that conforms to this interconnect protocol. OCP-IP (the IP here standards for International Partnership) is an industry association providing a common standard for IP core interfaces, or sockets, that facilitate "plug and play" System-on-Chip (SoC) design. Now be careful that you don’t read socket and think bus interface, because any number of bus interfaces can be used with this socket. OCP separates the computational IP core from its communications activity. Ian Mackintosh is the president and chairman of OCP-IP.

EDA Designline: In April of this year, OCP-IP released an enhanced version of their TLM kits. I asked Ian to expand on the importance of these kits.

Ian: The kits are important because we make them free to non-OCP-IP members, without the monitors, which is a very nice set of tools, for SoC designers, and also free with monitors to members. We’ve been shipping these things for 6.5 years. I couldn’t believe it, but I just double-checked on it, and we have literally ship thousands of copies – people have embedded these in their design systems over a long period of time. I think a lot of people even use older revisions. They’re nice because anyone using these kits, you can literally save yourselves hundreds of thousands of dollars in development costs, so they’re very nice. We’ve produced a version that has some updates and enhancements in them: they’re all TLM 2.0 compliant, and they have a greater robustness of data and payload event queues; a modification of thread busy signaling API; and then we’ve added support for interrupts, we’ve added sideband error signaling, and sideband user-flex. And importantly, we’ve added TLM to native adapters, between TL3 and TL1, and added TLM2 to native adapters between TL1 and RTL signals.

EDA Designline: What are the licensing terms on them?

Ian: People can take them under an RLA, members, actually, you’ve actually asked a very pertinent question. We make them available under an RLA for anybody who wants to take a copy, and you don’t even have to be a member. But we also have a very comprehensive licensing for member companies to accommodates very complex needs they have to work with contractors and any folks they hire or whatever, and it allows them to be able to move the data in and out of design systems without being compromised by any intellectual property rights issues. So we have a very sophisticated and comprehensive license that meets the needs of large corporations to manage their complex business and engineering development environments.

EDA Designline: Let’s move on to the OCP 3.1 release.

Ian: This is a big deal. The member review was completed at the end of June, and then will go into the formal release based on any inputs or additions we got. Paying members now have access to that specification. The new specification is different from the old one, inasmuch as we’ve taken all the verification and tests and checks that were embedded in the 3.0 version, and split them out into a compliance document. This is important because what we want to make that available for sale, so people can buy the thing even if they choose not to become a paying member. The types of features that we’ve added include flexible memory barriers. Right now, in the real world of design, you’ve got a need to have a deep pipelining of memory to cover the very high latency of external DRAM and that exposes complex ordering situations where you may have one core seem as if the memory is inconsistent with respect to operations of another core. So we’ve introduced memory barriers. Basically, this enables some of the performance-enhancing features of OCP, so that we enforce a system ordering and all the other cores can see the effects of the critical memory updates in the expected order.

The next thing we’ve added is transaction counting parameters. There is an analogous issue here because OCP supports very deep transaction pipelining across several request and response stages. It is really valuable to understand the number of outstanding transactions that each side of the interface can manage. This transaction counting parameter extension in 3.1 facilitates things like automatically transaction buffer sizing, protocol checking and formal verification of the interfaces based on a maximum transaction count supported for each tag, thread and interface.

The next thing that we’ve added is we’ve moved from a proprietary format, with our OCP RTL .com files to fully support the Accellera IP-XACT metadata format. This enables the integration of the OC compliant cores into an IP-XACT design environment.

The last but not least in terms of addition is some changes to cache coherency checking.  We introduced this in the 4th quarter of 2009. What we’ve added is the test and checking material to support compliance and to support checks on cache coherency.

EDA Designline: What about the benchmarking work?

Yes - we have a Network on Chip (NoC) benchmark networking group, which generated a lot of capabilities to be able to benchmark NoCs. We’ve developed a two-part spec, that enables you specify a NoC then define how to benchmark it and what should be benchmarked. One of the tools we’ve made available is called a transaction generator package. In that package, we have a set of nine traffic models for multimedia and telecom situations. Plus bundled with the package is also an accurate DRAM model, and oddly enough, no such thing previously existed. This accurate DRAM model allows me to look at the performance in a NoC because it accounts for the congestion and traffic, real traffic flow, around the memory access.  This is available through a GNU LPGL licensing, so it’s completely free to members and non-members alike. What you can also download with it, is what we call MCSL, or multi-core system-level traffic patterns, there are eight sets of patterns, which we’ve just obtained from the Hong Kong University of Science and Technology. Now the reason that this is very interesting is because they’re truly real-world traffic patterns. We have many other Universities that are working with us in this area.

EDA Designline: And last but not least is the new book.

The Introduction to the Open Core Protocol: Fastpath to System-on-Chip Design.

This is an introductory pack for new users and university people; it’s also a very important reference for experienced users. For these users, they can flick into it and bone up on things. The purpose of the book is to provide you with insights into the reasoning behind things – why they’re done that way and so on.

EDA Designline: I also heard that you personally have been working on a book, but that will have to wait for another blog. 

Book review: Empower your Inner Manager