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EDA/IP Weekly Roundup – October 10th
Brian Bailey
10/10/2012 11:05 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Distinguished UC-Berkeley Professor Jan M. Rabaey will deliver the keynote at a Low-Power Technology Summit sponsored by Cadence. Rabaey, author of "Low-Power Design Essentials," will address power issues that impact today's chip designers at the one-day technical conference on Oct. 18. For the complete agenda, visit the Cadence Web site.
Synopsys today completed the acquisition of EVE. Emulation is a rapidly growing solution in the spectrum of technologies used to verify today's highly complex systems on chips (SoCs). Integrating EVE's technology with Synopsys' platform of simulation, debug, verification IP (VIP), coverage, static verification, low power verification, FPGA prototyping and virtual prototyping solutions will give Synopsys customers access to a broad range of verification offerings. The terms of the acquisition have not been disclosed. Synopsys does not expect the transaction to have a material impact on its financial results in 2012 or 2013.
Kilopass Technology has appealed both the patent infringement case as well as the tort case against Sidense. On Kilopass’ request the Court issued an appealable judgment, and the case will be heard by the special patent court, the U.S. Court of Appeals for the Federal Circuit in Washington D.C. The appeal process will take approximately 9 – 12 months.
Cadence has introduced the Incisive® Debug Analyzer, a verification debug product for RTL, testbench and SoC verification that promises reductions in debug time and effort. According to Cadence, customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.
TSMC has announced that the readiness of 20nm and CoWoSTM design support within the Open Innovation Platform (OIP) is demonstrated by the delivery of two foundry-first reference flows supporting 20nm and CoWoSTM (Chip on Wafer on Substrate) technologies. TSMC’s 20nm Reference Flow enables double patterning technology (DPT) design using proven design flows. The new CoWoSTM Reference Flow that enables multi-die integration to support high bandwidth, low power can achieve fast time-to-market for 3D IC designs. The CoWoSTM flow also benefits designers by allowing them to use existing, mainstream tools from leading EDA vendors.
CEVA and NXP Software have partnered to deliver an enhanced HD voice processing solution for the smartphone market, integrating NXP Software’s LifeVibes VoiceExperience software with the CEVA-TeakLite family of DSPs, including the CEVA-TeakLite-4. NXP Software has ported and optimized its technologies in speakerphone and multi-microphone noise suppression, acoustic echo cancellation and voice quality. The CEVA-specific implementation of NXP Software’s VoiceExperience enables them to easily add HD quality voice processing technology into their existing designs. For licensees of the CEVA-TeakLite-III and CEVA-TeakLite-4 DSPs, the VoiceExperience algorithms can further harness the low power, native 32-bit, high performance voice capabilities to deliver better voice clarity and extended battery life.
Synopsys has announced the availability of CODE V® Optical Design Software, version 10.5, which offers new and improved optimization and tolerancing capabilities for the design of high-performance optical systems with reduced sensitivity to manufacturing and alignment errors. This helps designers create systems in CODE V that not only perform as specified, but are also less expensive to manufacture and can be assembled faster.
The Interoperable PDK Libraries (IPL) Alliance announced today that Solido Design Automation Inc., an electronic design automation (EDA) software provider for variation-aware custom integrated circuit (IC) design, has joined the IPL Alliance, a standards organization whose charter is to establish an interoperable custom design ecosystem. Solido Design Automation plans to support IPL's Interoperable Analog Design Constraint Standard 1.1. The IPL Alliance released the industry's first open standard for iPDKs for analog/mixed-signal designs in February 2010. The iPDK standard is based on the OpenAccess database and uses standard languages and a unified architecture to enable interoperability among all EDA vendor tools. IPL Alliance also released the standard for interoperable design constraints in June 2011.
To address the significant increase in data over the next 10-15 years, and the demand for more energy-efficient network infrastructure and servers, ARM has announced the ARM® CoreLink™ CCN-504 cache coherent network. This system intellectual property (IP) can deliver up to one terabit of usable system bandwidth per second. It will enable SoC designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and next-generation 64-bit processors.
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan® DDR4/3 PHY IP planned for introduction in 2013.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Distinguished UC-Berkeley Professor Jan M. Rabaey will deliver the keynote at a Low-Power Technology Summit sponsored by Cadence. Rabaey, author of "Low-Power Design Essentials," will address power issues that impact today's chip designers at the one-day technical conference on Oct. 18. For the complete agenda, visit the Cadence Web site.
Synopsys today completed the acquisition of EVE. Emulation is a rapidly growing solution in the spectrum of technologies used to verify today's highly complex systems on chips (SoCs). Integrating EVE's technology with Synopsys' platform of simulation, debug, verification IP (VIP), coverage, static verification, low power verification, FPGA prototyping and virtual prototyping solutions will give Synopsys customers access to a broad range of verification offerings. The terms of the acquisition have not been disclosed. Synopsys does not expect the transaction to have a material impact on its financial results in 2012 or 2013.
Kilopass Technology has appealed both the patent infringement case as well as the tort case against Sidense. On Kilopass’ request the Court issued an appealable judgment, and the case will be heard by the special patent court, the U.S. Court of Appeals for the Federal Circuit in Washington D.C. The appeal process will take approximately 9 – 12 months.
Cadence has introduced the Incisive® Debug Analyzer, a verification debug product for RTL, testbench and SoC verification that promises reductions in debug time and effort. According to Cadence, customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.
TSMC has announced that the readiness of 20nm and CoWoSTM design support within the Open Innovation Platform (OIP) is demonstrated by the delivery of two foundry-first reference flows supporting 20nm and CoWoSTM (Chip on Wafer on Substrate) technologies. TSMC’s 20nm Reference Flow enables double patterning technology (DPT) design using proven design flows. The new CoWoSTM Reference Flow that enables multi-die integration to support high bandwidth, low power can achieve fast time-to-market for 3D IC designs. The CoWoSTM flow also benefits designers by allowing them to use existing, mainstream tools from leading EDA vendors.
CEVA and NXP Software have partnered to deliver an enhanced HD voice processing solution for the smartphone market, integrating NXP Software’s LifeVibes VoiceExperience software with the CEVA-TeakLite family of DSPs, including the CEVA-TeakLite-4. NXP Software has ported and optimized its technologies in speakerphone and multi-microphone noise suppression, acoustic echo cancellation and voice quality. The CEVA-specific implementation of NXP Software’s VoiceExperience enables them to easily add HD quality voice processing technology into their existing designs. For licensees of the CEVA-TeakLite-III and CEVA-TeakLite-4 DSPs, the VoiceExperience algorithms can further harness the low power, native 32-bit, high performance voice capabilities to deliver better voice clarity and extended battery life.
Synopsys has announced the availability of CODE V® Optical Design Software, version 10.5, which offers new and improved optimization and tolerancing capabilities for the design of high-performance optical systems with reduced sensitivity to manufacturing and alignment errors. This helps designers create systems in CODE V that not only perform as specified, but are also less expensive to manufacture and can be assembled faster.
The Interoperable PDK Libraries (IPL) Alliance announced today that Solido Design Automation Inc., an electronic design automation (EDA) software provider for variation-aware custom integrated circuit (IC) design, has joined the IPL Alliance, a standards organization whose charter is to establish an interoperable custom design ecosystem. Solido Design Automation plans to support IPL's Interoperable Analog Design Constraint Standard 1.1. The IPL Alliance released the industry's first open standard for iPDKs for analog/mixed-signal designs in February 2010. The iPDK standard is based on the OpenAccess database and uses standard languages and a unified architecture to enable interoperability among all EDA vendor tools. IPL Alliance also released the standard for interoperable design constraints in June 2011.
To address the significant increase in data over the next 10-15 years, and the demand for more energy-efficient network infrastructure and servers, ARM has announced the ARM® CoreLink™ CCN-504 cache coherent network. This system intellectual property (IP) can deliver up to one terabit of usable system bandwidth per second. It will enable SoC designers to provide high-performance, cache coherent interconnect for ‘many-core’ enterprise solutions built using the ARM Cortex™-A15 MPCore™ processor and next-generation 64-bit processors.
ARM has also unveiled the new ARM CoreLink DMC-520 dynamic memory controller that has been designed and optimized to work with the CoreLink CCN-504. The new dynamic memory controller provides a high-bandwidth interface to shared off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. It is part of an integrated ARM DDR4 interface solution incorporating ARM Artisan® DDR4/3 PHY IP planned for introduction in 2013.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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