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EDA/IP weekly roundup – October 24th
Brian Bailey
10/24/2012 11:30 AM EDT
This is a roundup of news or activities in the past few days that may be of interest to people.
Moortec Semiconductor Limited announces their embedded die sensor range of IP targeting Process, Voltage and Temperature (PVT) sensing applications for 40-nanometer (nm) and 28-nm CMOS technologies. Moortec's range of precision analog IP for low-geometry technologies allows developers to sense on-chip conditions, optimizing large scale semiconductor device performance and enhancing the design flow of System on Chip (SoC) developments. Although the IP range is predominantly analog in design, the digital interfacing and standard CMOS process compatibility means they are easy to integrate within any digital implementation flow.
Tanner EDA and Israeli distributor New ARTech Technologies will hold a day-long conference on micro-electro-mechanical systems (MEMS) in Israel on 30 October 2012. This conference will feature presentations by Tanner EDA customers and partners along with briefs on Tanner EDA and SoftMEMS tools. SoftMEMS provides the CAD design environment used for the development and test of MEMS products.
Uniquify has successfully implemented the physical design of a low-power, low-cost 10Gb Ethernet controller integrated circuit (IC) for Tehuti Networks. The project was divided between register transfer level (RTL) code developed by Tehuti and the physical implementation of the TN4010 single port 10GbE controller from RTL to GDSII by Uniquify. Additionally, Uniquify sourced, qualified and integrated IP from two third-party vendors into the design including PCIe and Xaui SERDES and a phase lock loop (PLL) customized to meet Tehuti’s specific requirements. Uniquify delivered the final RTL to tapeout in two weeks using Perseus™, an automated proprietary SoC design management system it developed, meeting all area, power and performance goals.
STMicroelectronics, Soitec and CMP today announced that ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.
UMC has qualified the foundry industry's first high voltage embedded flash (eFlash) process that incorporates a true 12-volt solution. This 12V process enables single chip integration with improved signal-to-noise ratio (SNR) for mid to large panel touch screen applications by combining the HV component that drives the sensor elements with the eFlash memory that stores the control algorithm.
Cadence has made some enhancements to its Allegro® 16.6 Package Designer and System-in-Package (SiP) Layout solution that support low-profile IC package requirements for next-generation smartphones, tablets, and ultra-thin notebook PCs. New features in Allegro 16.6 Package Designer and Cadence® SiP Layout include open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package (WLCSP) capability.
Synopsys has announced that IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (DRC) and layout-vs.-schematic (LVS) runsets to UMC customers. IC Validator, part of the Galaxy™ Implementation Platform, is an add-on to IC Compiler™ for in-design physical verification.
IAR Systems has announced new functionality in its development tools for Renesas Electronics Corporation’s R32C and 78K microcontrollers. The updates include a new editor and source browser, which enables features such as auto-completion, code folding, block selection, block indentation, bracket matching, and zooming. The latest version of IAR Embedded Workbench® for R32C also adds integration with the version control system Subversion. The integration allows users to perform Subversion commands from within the IAR Embedded Workbench IDE, and to see the current status of project files and folders.
Renesas has announced the availability of a solution kit for low-power display technology. It combines an RL78 low-power MCU, software drivers and a low-power E Ink segmented display. The solution can operate at near zero power in applications like wireless sensors, industrial gauges, battery and memory level indicators. The Solution Kit, part number: YLPDSKRL78EINK is available now from Renesas and authorized distributors for $49 each. For locations and immediate delivery please visit: am.renesas.com/rl78eink.
Renesas has also introduced Smart Analog. Modern sensor devices require tuning of circuitry to convert the analog signals produced by the sensor itself into a signal appropriate for a microcontroller’s (MCU) analog-to-digital converter (ADC) subsystem. This iterative tuning process is time-consuming, adversely affecting time-to-market for most projects. The Smart Analog technology implements a range of analog front end topologies designed to be easily programmed to support various types of sensors with a single device. The technology uses a set of configurable amplifier circuits, which can be tailored using an intelligent and intuitive software GUI.
Xilinx has announced Vivado™ Design Suite 2012.3, offering new productivity enhancements for running the tools on multi-core processor workstations as well as new reference designs for speeding design implementation.
Sonics has unveiled the next generation of its SonicsGN™ (SGN) NoC – the latest product in the company’s portfolio of System IP that includes on-chip networks, memory and security subsystems, as well as SoC performance analysis tools. New features include I/O coherency, multichannel memory interleaving and security firewalls.
Mentor Graphics has announced the release of a new product in the HyperLynx® suite. The HyperLynx DRC product performs best practice design rule checking (DRC) on printed circuit board (PCB) layout databases. Driven by customizable rules, the HyperLynx DRC product can be executed by engineers and designers during the PCB layout process to highlight potential high-speed design issues pertaining to signal integrity, power integrity, and electromagnetic interference (EMI), without running detailed, time-consuming analysis.
Breker Verification has announced the latest release of its TrekSoC™ software that supports SoC designs containing multiple heterogeneous embedded processors. TrekSoC automatically generates self-verifying C test cases that run on the SoC’s processors in a fully synchronized manner for faster and more thorough verification. Its test cases exercise a wide range of functional scenarios, ensuring that the SoC can support the necessary concurrency, system-level and software functionality while meeting performance requirements.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Moortec Semiconductor Limited announces their embedded die sensor range of IP targeting Process, Voltage and Temperature (PVT) sensing applications for 40-nanometer (nm) and 28-nm CMOS technologies. Moortec's range of precision analog IP for low-geometry technologies allows developers to sense on-chip conditions, optimizing large scale semiconductor device performance and enhancing the design flow of System on Chip (SoC) developments. Although the IP range is predominantly analog in design, the digital interfacing and standard CMOS process compatibility means they are easy to integrate within any digital implementation flow.
Tanner EDA and Israeli distributor New ARTech Technologies will hold a day-long conference on micro-electro-mechanical systems (MEMS) in Israel on 30 October 2012. This conference will feature presentations by Tanner EDA customers and partners along with briefs on Tanner EDA and SoftMEMS tools. SoftMEMS provides the CAD design environment used for the development and test of MEMS products.
Uniquify has successfully implemented the physical design of a low-power, low-cost 10Gb Ethernet controller integrated circuit (IC) for Tehuti Networks. The project was divided between register transfer level (RTL) code developed by Tehuti and the physical implementation of the TN4010 single port 10GbE controller from RTL to GDSII by Uniquify. Additionally, Uniquify sourced, qualified and integrated IP from two third-party vendors into the design including PCIe and Xaui SERDES and a phase lock loop (PLL) customized to meet Tehuti’s specific requirements. Uniquify delivered the final RTL to tapeout in two weeks using Perseus™, an automated proprietary SoC design management system it developed, meeting all area, power and performance goals.
STMicroelectronics, Soitec and CMP today announced that ST’s CMOS 28nm Fully Depleted Silicon-On-Insulator (FD-SOI) process, which uses silicon substrates from Soitec, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. ST is releasing this process technology to third parties as it nears completion of its first commercial wafers.
UMC has qualified the foundry industry's first high voltage embedded flash (eFlash) process that incorporates a true 12-volt solution. This 12V process enables single chip integration with improved signal-to-noise ratio (SNR) for mid to large panel touch screen applications by combining the HV component that drives the sensor elements with the eFlash memory that stores the control algorithm.
Cadence has made some enhancements to its Allegro® 16.6 Package Designer and System-in-Package (SiP) Layout solution that support low-profile IC package requirements for next-generation smartphones, tablets, and ultra-thin notebook PCs. New features in Allegro 16.6 Package Designer and Cadence® SiP Layout include open cavity support for die placement, a new wirebond application mode that improves efficiency, and a wafer-level-chip-scale-package (WLCSP) capability.
Synopsys has announced that IC Validator physical verification product has been qualified by United Microelectronics Corporation for 28-nm physical signoff, with immediate availability of design rule checking (DRC) and layout-vs.-schematic (LVS) runsets to UMC customers. IC Validator, part of the Galaxy™ Implementation Platform, is an add-on to IC Compiler™ for in-design physical verification.
IAR Systems has announced new functionality in its development tools for Renesas Electronics Corporation’s R32C and 78K microcontrollers. The updates include a new editor and source browser, which enables features such as auto-completion, code folding, block selection, block indentation, bracket matching, and zooming. The latest version of IAR Embedded Workbench® for R32C also adds integration with the version control system Subversion. The integration allows users to perform Subversion commands from within the IAR Embedded Workbench IDE, and to see the current status of project files and folders.
Renesas has announced the availability of a solution kit for low-power display technology. It combines an RL78 low-power MCU, software drivers and a low-power E Ink segmented display. The solution can operate at near zero power in applications like wireless sensors, industrial gauges, battery and memory level indicators. The Solution Kit, part number: YLPDSKRL78EINK is available now from Renesas and authorized distributors for $49 each. For locations and immediate delivery please visit: am.renesas.com/rl78eink.
Renesas has also introduced Smart Analog. Modern sensor devices require tuning of circuitry to convert the analog signals produced by the sensor itself into a signal appropriate for a microcontroller’s (MCU) analog-to-digital converter (ADC) subsystem. This iterative tuning process is time-consuming, adversely affecting time-to-market for most projects. The Smart Analog technology implements a range of analog front end topologies designed to be easily programmed to support various types of sensors with a single device. The technology uses a set of configurable amplifier circuits, which can be tailored using an intelligent and intuitive software GUI.
Xilinx has announced Vivado™ Design Suite 2012.3, offering new productivity enhancements for running the tools on multi-core processor workstations as well as new reference designs for speeding design implementation.
Sonics has unveiled the next generation of its SonicsGN™ (SGN) NoC – the latest product in the company’s portfolio of System IP that includes on-chip networks, memory and security subsystems, as well as SoC performance analysis tools. New features include I/O coherency, multichannel memory interleaving and security firewalls.
Mentor Graphics has announced the release of a new product in the HyperLynx® suite. The HyperLynx DRC product performs best practice design rule checking (DRC) on printed circuit board (PCB) layout databases. Driven by customizable rules, the HyperLynx DRC product can be executed by engineers and designers during the PCB layout process to highlight potential high-speed design issues pertaining to signal integrity, power integrity, and electromagnetic interference (EMI), without running detailed, time-consuming analysis.
Breker Verification has announced the latest release of its TrekSoC™ software that supports SoC designs containing multiple heterogeneous embedded processors. TrekSoC automatically generates self-verifying C test cases that run on the SoC’s processors in a fully synchronized manner for faster and more thorough verification. Its test cases exercise a wide range of functional scenarios, ensuring that the SoC can support the necessary concurrency, system-level and software functionality while meeting performance requirements.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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