This is a roundup of news or activities in the past few days that may be of interest to people. Cadence
has announced the availability of an Automotive Ethernet Design IP and Verification IP (VIP) for the latest Automotive Ethernet Controllers. The standards-based Design IP and VIP support the latest Automotive Ethernet extensions as defined by the OPEN Alliance Special Interest Group (SIG). Together, both IP help speed today's newest automotive requirements to market, including improvements to in-vehicle safety, comfort, and infotainment as well as reductions in network complexity and cabling costs. Implementation of these new capabilities is made faster and easier by the Cadence® Media Access Controller (MAC) Design IP and VIP for Ethernet-based automotive connectivity.EDALab
has released a new version of HIFSuite. This allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages. This new version is more stable and robust than the previous ones and focuses on automatic translation and abstraction of hardware modules modeled in VHDL and Verilog into their SystemC equivalent.
Nominations are being accepted now through Jan 18 for the 2013 Accellera Systems Initiative Technical
Excellence Award. The Award recognizes outstanding contributions in the creation of electronic design automation (EDA) and intellectual property (IP) standards by a member of an Accellera technical committee. At DVCon earlier this year, John Aynsley was honored with the 2012 award for his contributions to the SystemC language. To nominate someone click here
. The award will be presented during a luncheon at Accellera Systems Initiative day, a part of DVCon 2013 taking place February 25-28, 2013 in San Jose, Calif.Atrenta
is expanding its sales and support operations in Israel with the addition of a dedicated sales manager and a customer solutions architect.
On Tuesday December 11 Cadence
is holding a free a webinar on "ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with ABVIP". As anyone who has worked with ARM's AMBA 4 AXITM Coherency Extensions -- a/k/a the "ACETM" protocol -- knows, there are a ton of different configuration options and operational scenarios available to the designer. Of course, this flexibility and power presents a significant verification challenge. RegisterIAR Systems
has announced a new product edition of Embedded Workbench® for RX tailored for small applications development. The Baseline edition is targeted at developers working with smaller memory Renesas RX MCUs and is offered at a price substantially reduced from that of the full edition. The Baseline edition is limited to a code size of 256 KB but provides full compiler and debugger functionality. IAR Systems is announcing the new edition alongside the latest version of IAR Embedded Workbench for RX, version 2.41.
A new white paper from ASSET® InterTech
, points out how increasing bus speeds on circuit boards could create havoc for signal integrity on those buses, in turn degrading the bus throughput performance. Each new generation of a high-speed bus typically runs at a higher signal frequency, but this decreases the margin for error on the bus, making it more sensitive to disruptions from jitter, inter-symbol interference (ISI), crosstalk and other factors.
The white paper, titled “Bandwidth tests reveal shrinking eye diagrams and signal integrity problems”, can be downloaded here
is proud to announce that it has received ISO 9001:2008 Management System Standard Certification from Det Norske Veritas (DNV). The DNV audit included eSilicon’s quality management system, quality system manual, management review process, review procedures, work instructions, production release process and records, physical silicon design and package design.Brian Bailey
– keeping you covered
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