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Verification is the Key Entrepreneurial Opportunity
Michel Courtoy
12/11/2012 10:55 AM EST
For a hardworking, creative and enterprising EDA entrepreneur, there is no shortage of technological challenges, especially on the verification front. The evolution of chips to big SoCs has made verification the most critical and time-consuming aspect of the development cycle. In many ways, it’s larger and more complex than hardware design.
This complexity is a big challenge and sometimes becomes a hurdle to the acceptance of newer, better technologies. Several years back, I visited a verification engineer when I was CEO of a small verification company. He politely listened to the presentation about our new technology and liked what he heard. He somewhat facetiously said that he liked the tool. However, he currently had 11 other tools running and asked me which one he could drop if he adopted my technology. His point was that he couldn’t handle another tool.
Few verification engineers would argue that verification closure is still an elusive goal. Despite the numerous weapons a verification engineer has in his or her arsenal, tapeouts are still mostly given the “green light” based on schedule constraints and with the knowledge that bugs remain in the design. The hope is that software patches will fix the remaining problems or that bugs are acceptable to end users. As an example, we all occasionally have to restart our smartphones, but it does not mean that we deem the device to be of poor quality.
Another manifestation of the incomplete closure offered by the plethora of verification tools is the increasing use of the shuttle services offered by silicon foundries. These shuttles are small volume, regularly scheduled fab runs split between many designs to reduce tooling costs (NRE of the mask set, mostly) for each participant.
Shuttles enable design and verification teams to create silicon prototypes early in the design cycle at a reduced cost. The benefit is that extensive tests can be run on the actual silicon at much higher speeds than in simulation, emulation or FPGA prototype. The requirement is, of course, that these initial chips must perform basic operations.
Let’s turn our attention to the opportunities for a hardworking, creative and enterprising individual who sees a future in solving the verification challenge. The semiconductor industry has many unsolved verification problems and clearly there’s a gap in verification coverage. That makes verification an exciting market where one key opportunity stands out in my mind –– that is, system-level verification.
Today, the state of the art in functional verification is considered to be the Universal Verification Methodology (UVM) based on constrained random tests. This approach is effective at the block or sub-system level, but does not scale well for SoCs with multiple embedded processors, and they are prevalent and gobbling up functionality in ultrabooks, smartphones, tablets and other cool devices.
This leaves verification teams with a large gap when it comes to SoC-level verification. For example, as a member of the Board of Directors at Breker Verification Systems, I often hear the expression, “Stitch and ship will sink you every time.” A catchy phrase, to be sure, but the message is clear: Today’s verification tools are only performing basic checks at the SoC level, including simple connectivity checks and basic “directed” C tests running on embedded processors. This leaves unaddressed the more complex checks required to ensure the operation of multi-processor SoCs.
What verification teams need is the ability to generate complex C tests running on embedded processors to exercise the corner cases of their most complex SoCs. This is the bridge between the simple hand-written directed C tests and running application software –– usually performed in emulation or prototyping. The former falls short in terms of coverage since it is impossible to write tests for the complex operations of a multi-processor SoC; the latter tends to result in well-behaved code.
Anyone thinking about starting a verification company must be wondering about the financing since the traditional venture capital route is not readily available any longer. Instead, many of the Silicon Valley companies I talk to are bootstrapping themselves through consulting contracts or borrowing from family members and friends of the family. As a more mature industry, EDA has several angel investors willing to invest in startups because they’ve been there and done it, and have the funds to pay it forward. Several companies have turned to corporate partners for an investment. Others have gone offshore for funding.
The formerly dependable exit strategy has changed as well. The big three EDA vendors have a different acquisition strategy than in the past when they gobbled up small companies with promising technology. Today, they are more likely to purchase a large company with a mature, stable product and a portfolio of paying customers. Who hadn’t heard that Magma was too big to be acquired?
Creativity, then, is a watchword for the product direction, funding and an exit strategy. Daunting challenges, no doubt, but not nearly as daunting as the challenges associated with today’s chip verification. An enterprising EDA entrepreneur will not be dissuaded and will agree with me that verification is an exciting market segment filled with loads of challenge.
About the author
Michel Courtoy is a Member of the Board of Directors of Breker Verification Systems. He began his career at Intel in design engineering and software engineering. He managed product marketing for layout verification software at Cadence Design Systems. As vice president of marketing for Silicon Perspective, Courtoy created the market for silicon virtual prototyping and was a key player in its acquisition by Cadence in 2001. He served as a vice president at Cadence before becoming the CEO at Certess, leading Certess through sales growth to a successful exit by acquisition. Courtoy holds a Bachelor of Science degree in electrical engineering from University Catholique de Louvain, Belgium; a Master of Science degree in Electrical Engineering from University of California, San Diego; and an MBA from Santa Clara University in Santa Clara, Calif.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
This complexity is a big challenge and sometimes becomes a hurdle to the acceptance of newer, better technologies. Several years back, I visited a verification engineer when I was CEO of a small verification company. He politely listened to the presentation about our new technology and liked what he heard. He somewhat facetiously said that he liked the tool. However, he currently had 11 other tools running and asked me which one he could drop if he adopted my technology. His point was that he couldn’t handle another tool.
Few verification engineers would argue that verification closure is still an elusive goal. Despite the numerous weapons a verification engineer has in his or her arsenal, tapeouts are still mostly given the “green light” based on schedule constraints and with the knowledge that bugs remain in the design. The hope is that software patches will fix the remaining problems or that bugs are acceptable to end users. As an example, we all occasionally have to restart our smartphones, but it does not mean that we deem the device to be of poor quality.
Another manifestation of the incomplete closure offered by the plethora of verification tools is the increasing use of the shuttle services offered by silicon foundries. These shuttles are small volume, regularly scheduled fab runs split between many designs to reduce tooling costs (NRE of the mask set, mostly) for each participant.
Shuttles enable design and verification teams to create silicon prototypes early in the design cycle at a reduced cost. The benefit is that extensive tests can be run on the actual silicon at much higher speeds than in simulation, emulation or FPGA prototype. The requirement is, of course, that these initial chips must perform basic operations.
Let’s turn our attention to the opportunities for a hardworking, creative and enterprising individual who sees a future in solving the verification challenge. The semiconductor industry has many unsolved verification problems and clearly there’s a gap in verification coverage. That makes verification an exciting market where one key opportunity stands out in my mind –– that is, system-level verification.
Today, the state of the art in functional verification is considered to be the Universal Verification Methodology (UVM) based on constrained random tests. This approach is effective at the block or sub-system level, but does not scale well for SoCs with multiple embedded processors, and they are prevalent and gobbling up functionality in ultrabooks, smartphones, tablets and other cool devices.
This leaves verification teams with a large gap when it comes to SoC-level verification. For example, as a member of the Board of Directors at Breker Verification Systems, I often hear the expression, “Stitch and ship will sink you every time.” A catchy phrase, to be sure, but the message is clear: Today’s verification tools are only performing basic checks at the SoC level, including simple connectivity checks and basic “directed” C tests running on embedded processors. This leaves unaddressed the more complex checks required to ensure the operation of multi-processor SoCs.
What verification teams need is the ability to generate complex C tests running on embedded processors to exercise the corner cases of their most complex SoCs. This is the bridge between the simple hand-written directed C tests and running application software –– usually performed in emulation or prototyping. The former falls short in terms of coverage since it is impossible to write tests for the complex operations of a multi-processor SoC; the latter tends to result in well-behaved code.
Anyone thinking about starting a verification company must be wondering about the financing since the traditional venture capital route is not readily available any longer. Instead, many of the Silicon Valley companies I talk to are bootstrapping themselves through consulting contracts or borrowing from family members and friends of the family. As a more mature industry, EDA has several angel investors willing to invest in startups because they’ve been there and done it, and have the funds to pay it forward. Several companies have turned to corporate partners for an investment. Others have gone offshore for funding.
The formerly dependable exit strategy has changed as well. The big three EDA vendors have a different acquisition strategy than in the past when they gobbled up small companies with promising technology. Today, they are more likely to purchase a large company with a mature, stable product and a portfolio of paying customers. Who hadn’t heard that Magma was too big to be acquired?
Creativity, then, is a watchword for the product direction, funding and an exit strategy. Daunting challenges, no doubt, but not nearly as daunting as the challenges associated with today’s chip verification. An enterprising EDA entrepreneur will not be dissuaded and will agree with me that verification is an exciting market segment filled with loads of challenge.
About the author
Michel Courtoy is a Member of the Board of Directors of Breker Verification Systems. He began his career at Intel in design engineering and software engineering. He managed product marketing for layout verification software at Cadence Design Systems. As vice president of marketing for Silicon Perspective, Courtoy created the market for silicon virtual prototyping and was a key player in its acquisition by Cadence in 2001. He served as a vice president at Cadence before becoming the CEO at Certess, leading Certess through sales growth to a successful exit by acquisition. Courtoy holds a Bachelor of Science degree in electrical engineering from University Catholique de Louvain, Belgium; a Master of Science degree in Electrical Engineering from University of California, San Diego; and an MBA from Santa Clara University in Santa Clara, Calif.If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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