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EDA/IP weekly roundup – December 12th
Brian Bailey
12/12/2012 11:00 AM EST
This is a roundup of news or activities in the past few days that may be of interest to people.
Agilent has announced shipment of Advanced Design System 2012, its RF and microwave EDA software platform. ADS 2012 features new capabilities that improve productivity and efficiency for all applications the system supports and breakthrough technologies applicable to GaAs, GaN and silicon RF power-amplifier multichip module design.
Real Intent has released a new version of its Ascent™ Lint software for early functional verification – which it claims is the industry’s fastest high-capacity, low-noise lint analyzer. This new version enhances complex bug detection early in design cycle. With 60 comprehensive new rules (including FSM checks among other rules) and expanded language support, it helps SoC designers find design errors, design style and coding errors to make sure their RTL code is correct and clean.
Synopsys achieved double-digit revenue and earnings per share growth in Q4 and FY2012 results, while maintaining a strong operating cash flow. Revenue for the Q4 2012 was $454.2 million, compared to $390.5 million for Q4 2011. GAAP net income for Q4 2012 was $29.1 million, or $0.19 per share, compared to $39.9 million, or $0.27 per share, for Q4 2011. Revenue for the full fiscal year 2012 was $1.756 billion, an increase of 14.3 percent from $1.536 billion in fiscal 2011. GAAP net income was $182.4 million, or $1.21 per share, compared to $221.4 million, or $1.47 per share, for fiscal 2011. Net income for fiscal 2012 included $43.6 million of acquisition-related costs, plus higher amortization of intangibles than in the previous year primarily due to acquisitions.
Newark element14 has launched an industrial automation microsite, developed to help engineers in design or plant maintenance roles more efficiently research and source products. The microsite at www.newark.com/industrialautomation offers information produced by Newark element14’s technical support team, plus the latest data and technology products from the world’s top suppliers, including Eaton, Honeywell, IDEC, Molex/Daniel Woodhead, Omron, Schneider Electric and TE Connectivity.
MIPS Technologies has announced a major release of the MIPS® architecture, encompassing the MIPS32®, MIPS64® and microMIPS™ instruction set architectures. Based on work done over more than two years, Release 5 ("R5") of the MIPS base architecture incorporates important functionality including virtualization and SIMD (Single Instruction Multiple Data) modules.
Mentor Graphics has announced the availability of its latest Embedded Sourcery™ VSIPL++ product. The Sourcery VSIPL++ product adds support for ARM v7 Cortex A with NEON single instruction, multiple data (SIMD) processing platforms, and an interface to MATLAB® for signal and image processing algorithm conversion. This MATLAB interface allows users to easily convert algorithm models into VSIPL++ compliant C++ code and to verify the correct function of the deployed code on a specific target system.
Last year, the market value of all the devices using TSV packaged in 3D in the 3DIC or 3D-WLCSP platforms (CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7B according to Research and Markets. It will represent 9% of the total semiconductor value by 2017, hitting almost $40B. 3DIC which typically uses TSV 'via middle' for memory and logic IC stacking is expected to grow the fastest in wafers as well as in overall value, whereas 3D WLCSP will continue growing at a 18% CAGR.
Imec and Synopsys have expanded their collaboration in the field of Technology Computer Aided Design (TCAD) to next-generation FinFET technology at 10 nm. The collaboration builds on extensive work done at 14 nm and several other process geometries, and will calibrate Synopsys' Sentaurus™ TCAD models to support the next-generation FinFET devices. The collaboration will include 3-D modeling of new device architectures and materials that will enable the semiconductor industry to continue to deliver products with higher performance and lower power consumption.
Oasys says that Scott Seaton has been named the company’s President and CEO. Mr. Seaton was also appointed a director of the company. Mr. Seaton succeeds founder Paul van Besouw who will become the company’s CTO and Chairman of its board of directors.
Altera has announced shipment of its 28 nm SoC devices, which combine a dual-core ARM® Cortex™-A9 processor system with FPGA logic on a single device. The first devices Altera is shipping are low-power, low-cost Cyclone® V SoCs.
Altera and ARM have jointly developed a DS-5 embedded software development toolkit with FPGA-adaptive debug capabilities for Altera SoC devices. The ARM® Development Studio 5 (DS-5™) Altera Edition toolkit is designed to remove the debugging barrier between the integrated dual-core CPU subsystem and FPGA fabric in Altera SoC devices. The new toolkit will be included in the Altera SoC Embedded Design Suite and will begin shipping in early 2013.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Agilent has announced shipment of Advanced Design System 2012, its RF and microwave EDA software platform. ADS 2012 features new capabilities that improve productivity and efficiency for all applications the system supports and breakthrough technologies applicable to GaAs, GaN and silicon RF power-amplifier multichip module design.
Real Intent has released a new version of its Ascent™ Lint software for early functional verification – which it claims is the industry’s fastest high-capacity, low-noise lint analyzer. This new version enhances complex bug detection early in design cycle. With 60 comprehensive new rules (including FSM checks among other rules) and expanded language support, it helps SoC designers find design errors, design style and coding errors to make sure their RTL code is correct and clean.
Synopsys achieved double-digit revenue and earnings per share growth in Q4 and FY2012 results, while maintaining a strong operating cash flow. Revenue for the Q4 2012 was $454.2 million, compared to $390.5 million for Q4 2011. GAAP net income for Q4 2012 was $29.1 million, or $0.19 per share, compared to $39.9 million, or $0.27 per share, for Q4 2011. Revenue for the full fiscal year 2012 was $1.756 billion, an increase of 14.3 percent from $1.536 billion in fiscal 2011. GAAP net income was $182.4 million, or $1.21 per share, compared to $221.4 million, or $1.47 per share, for fiscal 2011. Net income for fiscal 2012 included $43.6 million of acquisition-related costs, plus higher amortization of intangibles than in the previous year primarily due to acquisitions.
Newark element14 has launched an industrial automation microsite, developed to help engineers in design or plant maintenance roles more efficiently research and source products. The microsite at www.newark.com/industrialautomation offers information produced by Newark element14’s technical support team, plus the latest data and technology products from the world’s top suppliers, including Eaton, Honeywell, IDEC, Molex/Daniel Woodhead, Omron, Schneider Electric and TE Connectivity.
MIPS Technologies has announced a major release of the MIPS® architecture, encompassing the MIPS32®, MIPS64® and microMIPS™ instruction set architectures. Based on work done over more than two years, Release 5 ("R5") of the MIPS base architecture incorporates important functionality including virtualization and SIMD (Single Instruction Multiple Data) modules.
Mentor Graphics has announced the availability of its latest Embedded Sourcery™ VSIPL++ product. The Sourcery VSIPL++ product adds support for ARM v7 Cortex A with NEON single instruction, multiple data (SIMD) processing platforms, and an interface to MATLAB® for signal and image processing algorithm conversion. This MATLAB interface allows users to easily convert algorithm models into VSIPL++ compliant C++ code and to verify the correct function of the deployed code on a specific target system.
Last year, the market value of all the devices using TSV packaged in 3D in the 3DIC or 3D-WLCSP platforms (CMOS image sensors, Ambient light sensors, Power Amplifiers, RF and inertial MEMS) was worth $2.7B according to Research and Markets. It will represent 9% of the total semiconductor value by 2017, hitting almost $40B. 3DIC which typically uses TSV 'via middle' for memory and logic IC stacking is expected to grow the fastest in wafers as well as in overall value, whereas 3D WLCSP will continue growing at a 18% CAGR.
Imec and Synopsys have expanded their collaboration in the field of Technology Computer Aided Design (TCAD) to next-generation FinFET technology at 10 nm. The collaboration builds on extensive work done at 14 nm and several other process geometries, and will calibrate Synopsys' Sentaurus™ TCAD models to support the next-generation FinFET devices. The collaboration will include 3-D modeling of new device architectures and materials that will enable the semiconductor industry to continue to deliver products with higher performance and lower power consumption.
Oasys says that Scott Seaton has been named the company’s President and CEO. Mr. Seaton was also appointed a director of the company. Mr. Seaton succeeds founder Paul van Besouw who will become the company’s CTO and Chairman of its board of directors.
Altera has announced shipment of its 28 nm SoC devices, which combine a dual-core ARM® Cortex™-A9 processor system with FPGA logic on a single device. The first devices Altera is shipping are low-power, low-cost Cyclone® V SoCs.
Altera and ARM have jointly developed a DS-5 embedded software development toolkit with FPGA-adaptive debug capabilities for Altera SoC devices. The ARM® Development Studio 5 (DS-5™) Altera Edition toolkit is designed to remove the debugging barrier between the integrated dual-core CPU subsystem and FPGA fabric in Altera SoC devices. The new toolkit will be included in the Altera SoC Embedded Design Suite and will begin shipping in early 2013.
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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