Samsung and partners create 14nm FinFET test chips

12/21/2012 11:45 AM EST

Over the past couple of days there have been a string of press releases related to the tape-out of a test chip from Samsung at 14nm using FinFETs. This is a condensation of those releases from Samsung, ARM, Cadence, Synopsys and Mentor.

Samsung announced that a milestone in the development of 14-nanometer (nm) FinFET process technology with the successful tape-out of multiple development vehicles in collaboration with its key design and IP partners. In addition, Samsung has signed an agreement with ARM® for 14nm physical IP and libraries. As part of its 14nm FinFET development process, Samsung, and its ecosystem partners – ARM, Cadence, Mentor and Synopsys – taped out multiple test chips ranging from a full ARM® Cortex™-A7 processor implementation to a SRAM-based chip capable of operation near threshold voltage levels as well as an array of analog IP.

Along with that, ARM and Cadence have announced the tape-out of the first 14-nanometer test chip implementation of the high-performance ARM® Cortex™-A7 processor. Designed with a complete Cadence® RTL-to-signoff flow, the chip is the first to target Samsung's 14-nanometer FinFET process, accelerating the continuing move to high-density, high-performance and ultra-low power SoCs for future smartphones, tablets and all other advanced mobile devices. In addition to the ARM Cortex-A7 processor, the test chip includes ARM Artisan® standard-cell libraries, next-generation memories, and general purpose IOs.

Synopsys announced that its multi-year collaboration with Samsung on FinFET technology has achieved a critical milestone: the successful tapeout of the first test chip on Samsung's 14LPE process. While the FinFET process offers significant power and performance benefits compared to the traditional planar process, the move from two-dimensional transistors to three-dimensional transistors introduces several new IP and EDA tool challenges such as modeling. The multi-year collaboration delivered the foundational modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices. Synopsys' comprehensive solution for embedded memory, physical design, parasitic extraction, timing analysis and signoff is built on this foundation.

Mentor Graphics announced comprehensive design, manufacturing, and post tapeout enabling support for Samsung’s 14nm IC manufacturing processes. The Calibre platform creates decomposed double patterning (DP) layouts that are compliant with all of Samsung’s 14nm lithography requirements and tuned to the Samsung mask synthesis and OPC process, which is also provided by Mentor at 14nm. It provides feedback on complex design rules for FinFETs, and specific coaching on elimination of DFM litho errors. Calibre tools for LVS and extraction have been calibrated to ensure accurate device and parasitic models for Samsung FinFETs, eliminating “double-counting” of important effects that can occur with other tools. Calibre SmartFill ensures there are no CMP issues with designs. They are also leveraging production test diagnosis by exchanging information between the Tessent tools and the Calibre Pattern Matching facility to quickly identify and eliminate design-specific yield limiting features during design ramp up.