EDA DesignLine Blog
Tell us What You Think
We want to know what you thought about this Discussion. Let us know by adding a comment.
EDA/IP weekly roundup – January 2nd 2013
Brian Bailey
1/2/2013 11:43 AM EST
This is a roundup of news or activities in the past few days that may be of interest to people.
Mentor Graphics has announced a solution to design network-based devices for machine-to-machine (M2M) and smart energy applications with the latest release of the Mentor® Embedded Nucleus® Real Time Operating System (RTOS) platform. Embedded developers can design auto configuring network devices for environments without supporting infrastructure, such as network servers, with the addition of mDNS and DNS-Service Discovery (SD) support to the Nucleus RTOS.
Xilinx says its Vivado™ Design Suite is now available in WebPACK Edition, giving designers immediate access to a no cost, device-limited version of the industry’s first SoC strength design environment. Offered with the 2012.4 release of the Vivado Design Suite, WebPACK Edition provides the same IP and system-centric design flows of the Vivado Design Suite Design edition that enables up to 4x faster time to integration and implementation over alternatives. The Vivado Design Suite, WebPACK Edition is a free download that provides support for Artix™-7 100T and 200T and Kintex™-7 70T and 160T devices.
While I don’t usually report on tools being adopted by companies, there were some interesting statements in this one, so excerpts of it are included here. Mahesh Tirupattur, executive vice president at Analog Bits said that “As process nodes shrink, electromigration is becoming a bigger and bigger problem. Metal becomes thinner and narrower, so that more sophisticated wiring is needed, making layout more complex. Layout-driven design is now vital to see how power distribution should be implemented. To complete the other side of the picture, John Zuk, vice president of marketing and business strategy at Tanner EDA says that “The market tells us that, starting at 28 nm, analog layout becomes about 3-5x more complicated for IC design.”
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
Mentor Graphics has announced a solution to design network-based devices for machine-to-machine (M2M) and smart energy applications with the latest release of the Mentor® Embedded Nucleus® Real Time Operating System (RTOS) platform. Embedded developers can design auto configuring network devices for environments without supporting infrastructure, such as network servers, with the addition of mDNS and DNS-Service Discovery (SD) support to the Nucleus RTOS.
Xilinx says its Vivado™ Design Suite is now available in WebPACK Edition, giving designers immediate access to a no cost, device-limited version of the industry’s first SoC strength design environment. Offered with the 2012.4 release of the Vivado Design Suite, WebPACK Edition provides the same IP and system-centric design flows of the Vivado Design Suite Design edition that enables up to 4x faster time to integration and implementation over alternatives. The Vivado Design Suite, WebPACK Edition is a free download that provides support for Artix™-7 100T and 200T and Kintex™-7 70T and 160T devices.
While I don’t usually report on tools being adopted by companies, there were some interesting statements in this one, so excerpts of it are included here. Mahesh Tirupattur, executive vice president at Analog Bits said that “As process nodes shrink, electromigration is becoming a bigger and bigger problem. Metal becomes thinner and narrower, so that more sophisticated wiring is needed, making layout more complex. Layout-driven design is now vital to see how power distribution should be implemented. To complete the other side of the picture, John Zuk, vice president of marketing and business strategy at Tanner EDA says that “The market tells us that, starting at 28 nm, analog layout becomes about 3-5x more complicated for IC design.”
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
|
|
|
|
|
Navigate to related information