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Top 5 memory trends for 2013
Kristin Lewotsky
1/8/2013 2:17 PM EST
The need for speed—DDR4 and LPDDR3
Whether the application is smart phones, PCs, or enterprise storage, the only memory characteristic more important than density is speed. September saw the official release of the DDR4 DRAM standard from JEDEC. The current version of the standard is based on a per-pin data rate of 1.6 GT/s, with an initial maximum objective of 3.2 GT/s. Now, there was some quibbling at the time of release about the fact that the starting data rate of 1.6 GT/s is already being delivered by DDR3 devices. That’s less a knock on DDR4 than a tribute to the work done by vendors and the standards team on DDR3, though—remember, when DDR3 debuted in 2007, its initial speed was 0.8 GT/s. The DDR4 team has loftier aims than 3.2 GT/s, so look for new versions of the standard to come out on a regular basis.
Recognizing the market shift toward portable devices, the DDR4 team focused much of their effort on adding refinements to reduce power consumption. The standard calls for a supply voltage of just 1.2 V compared to 1.8 V for DDR2.
Speaking of specifications for low-power devices, 2012 also saw the release of JEDEC’s latest low-power DRAM standard, LPDDR3. With a focus on write-leveling, CA training, and on-die termination, LPDDR3 gives the community the tools they need to develop memory products for the mobile device industry.
In the case of both standards, vendors like SK Hynix, Samsung, Cadence, and Micron Technologies had put out products well before the formal release of the documents. For now, DDR3 and LPDDR2 are still the workhorse technologies, but look for that to change.
Next: 3-D memory
Whether the application is smart phones, PCs, or enterprise storage, the only memory characteristic more important than density is speed. September saw the official release of the DDR4 DRAM standard from JEDEC. The current version of the standard is based on a per-pin data rate of 1.6 GT/s, with an initial maximum objective of 3.2 GT/s. Now, there was some quibbling at the time of release about the fact that the starting data rate of 1.6 GT/s is already being delivered by DDR3 devices. That’s less a knock on DDR4 than a tribute to the work done by vendors and the standards team on DDR3, though—remember, when DDR3 debuted in 2007, its initial speed was 0.8 GT/s. The DDR4 team has loftier aims than 3.2 GT/s, so look for new versions of the standard to come out on a regular basis.
Recognizing the market shift toward portable devices, the DDR4 team focused much of their effort on adding refinements to reduce power consumption. The standard calls for a supply voltage of just 1.2 V compared to 1.8 V for DDR2.
Speaking of specifications for low-power devices, 2012 also saw the release of JEDEC’s latest low-power DRAM standard, LPDDR3. With a focus on write-leveling, CA training, and on-die termination, LPDDR3 gives the community the tools they need to develop memory products for the mobile device industry.
In the case of both standards, vendors like SK Hynix, Samsung, Cadence, and Micron Technologies had put out products well before the formal release of the documents. For now, DDR3 and LPDDR2 are still the workhorse technologies, but look for that to change.
Next: 3-D memory
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DadOf3TeenieBoppers
1/14/2013 11:55 AM EST
The main problem with SSDs is wearing them out from the continuous writing to the index tables. The solution is to design a multi-technology SSD; a CMOS RAM based area where the indexes are stored and then the non-volatile memory for the data files themselves.
During a loss of power the SSD will need sufficient capacitive storage to copy the CMOS RAM to some NV memory. When power is restored, the CMOS is reloaded from NV RAM and the disk is ready to operate.
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DadOf3TeenieBoppers
1/14/2013 11:59 AM EST
I have worked on requirements for airborne military computers. Customers do not like using capacitors to maintain CMOS RAM when power is down. But they generally do not have a problem using capacitors to store enough charge to copy volatile memory to NVM when power goes down. In addition, some simple algorithms can be developed that copy those parts of CMOS RAM to NVM that have been updated by do not appear to be changing that much, leaving the task of saving those parts of CMOS that do change frequently only when power goes out.
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selinz
2/12/2013 2:06 PM EST
The PC is still the center of the universe for most. Phones are much more capable but nobody would even consider buying a PC with the current technical limitations of a phone on storage, bandwidth, and processing power. Not to mention the screen, although the ability to hook up to HD TV's really obviates this limitation.
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R G.Neale
2/12/2013 7:52 PM EST
Relative success at the very leading edge of non-volatile memory development challenging Flash,i.e.MRAM, PCM, FeRAM ReRAM, CBRAM CNT-RAM etc. can only really be measured by a league table of design-in wins. In the past claims and counter claims that are for the most part the chatter of promoters selling futures have plagued many NV technology developments. More recently the claim, see
http://www.eetimes.com/electronics-news/4401477/Electronica--Micron-memory-to-skip-a-node
Quote “………Micron will ship tens of millions of units of 1-Gbit PCM in 2012 in 45-nm process in its leading-edge component, which combines a 1-Gbit PCM die with a 512-Mbit SDRAM and provides a LPDDR2 interface………”
A claim that was associated with an actual design win that has needed the near term shipping numbers to be modified down wards when more closely scrutinized by us. It was a claim that perhaps had more to do with enthusiasm than reality.
So please, bring on the design-in wins league table as the way of providing true measure of NV memory potential and success.
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