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Top 5 memory trends for 2013
Kristin Lewotsky
1/8/2013 2:17 PM EST
3-D memory
Like the bogeyman in the closet, the memory wall is lurking out there in the future. Unfortunately, unlike the bogeyman, the memory wall isn’t hidden away or a figment of our imagination but a real problem that draws closer with every passing month. Building up instead of out provides a solution. Enter the hybrid memory cube, which takes memory 3-D in order to provide high-speed, high-efficiency performance in a space 90% smaller than for today’s RDIMMs.
The first draft of the standard came out last summer and focused on interface protocol and short-reach interconnection across the physical layer (PHY). The next step is to define an ultra-short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs. Look for progress to accelerate over the course of the coming year. Twenty bucks goes to the first person who can find a 2013 memory conference that doesn’t have at least one paper talking about 3-D memory.
Next: Enterprising drives
The first draft of the standard came out last summer and focused on interface protocol and short-reach interconnection across the physical layer (PHY). The next step is to define an ultra-short-reach PHY for applications requiring tightly coupled or close proximity memory support for FPGAs, ASICs and ASSPs. Look for progress to accelerate over the course of the coming year. Twenty bucks goes to the first person who can find a 2013 memory conference that doesn’t have at least one paper talking about 3-D memory.
Next: Enterprising drives
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DadOf3TeenieBoppers
1/14/2013 11:55 AM EST
The main problem with SSDs is wearing them out from the continuous writing to the index tables. The solution is to design a multi-technology SSD; a CMOS RAM based area where the indexes are stored and then the non-volatile memory for the data files themselves.
During a loss of power the SSD will need sufficient capacitive storage to copy the CMOS RAM to some NV memory. When power is restored, the CMOS is reloaded from NV RAM and the disk is ready to operate.
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DadOf3TeenieBoppers
1/14/2013 11:59 AM EST
I have worked on requirements for airborne military computers. Customers do not like using capacitors to maintain CMOS RAM when power is down. But they generally do not have a problem using capacitors to store enough charge to copy volatile memory to NVM when power goes down. In addition, some simple algorithms can be developed that copy those parts of CMOS RAM to NVM that have been updated by do not appear to be changing that much, leaving the task of saving those parts of CMOS that do change frequently only when power goes out.
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selinz
2/12/2013 2:06 PM EST
The PC is still the center of the universe for most. Phones are much more capable but nobody would even consider buying a PC with the current technical limitations of a phone on storage, bandwidth, and processing power. Not to mention the screen, although the ability to hook up to HD TV's really obviates this limitation.
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R G.Neale
2/12/2013 7:52 PM EST
Relative success at the very leading edge of non-volatile memory development challenging Flash,i.e.MRAM, PCM, FeRAM ReRAM, CBRAM CNT-RAM etc. can only really be measured by a league table of design-in wins. In the past claims and counter claims that are for the most part the chatter of promoters selling futures have plagued many NV technology developments. More recently the claim, see
http://www.eetimes.com/electronics-news/4401477/Electronica--Micron-memory-to-skip-a-node
Quote “………Micron will ship tens of millions of units of 1-Gbit PCM in 2012 in 45-nm process in its leading-edge component, which combines a 1-Gbit PCM die with a 512-Mbit SDRAM and provides a LPDDR2 interface………”
A claim that was associated with an actual design win that has needed the near term shipping numbers to be modified down wards when more closely scrutinized by us. It was a claim that perhaps had more to do with enthusiasm than reality.
So please, bring on the design-in wins league table as the way of providing true measure of NV memory potential and success.
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