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Hogan says retooling underway for custom 2.0
James Hogan
1/11/2013 11:53 AM EST
The “Custom 1.0” era began around 1980 and has had a run for over three decades. The early SPICE engines were mostly close cousins with UC Berkeley SPICE and ran on mainframes. Cadence Analog Artist was the first successful commercial solution for Custom 1.0, tying schematics to simulation and annotating simulation results to the schematic. Analog Artist has evolved to become Cadence Analog Design Environment (ADE) and still dominates the market today.
The time has come to re-architect both the environment and the simulators to meet the challenges confronting custom design today. The semiconductor industry is now facing a major retooling for “Custom 2.0” for 2013 and beyond.
Custom 2.0 retooling - drivers and outlook
The fierce competition to supply low-power, low-cost, gigahertz frequencies consumer devices is driving a move to sub-28 nm processes. All this is coupled with the need for a fast yield ramp to volume. However, while transistors are shrinking, atoms aren’t. Just a few out-of-place atoms can cause severe variability in a device, which translates into severe variability in analog/mixed-signal (AMS) and memory circuits, ultimately affecting the whole chip’s power, performance, and yield. The complexity is further exacerbated by 3D transistors.
Meeting the power, performance and area demands requires a step function change. SoCs need the latest process generations at 28nm, 20nm, and below. Somehow, the SoCs must deal with variability and all the other challenges wrought by the smaller nodes, as the percentage of embedded memory and analog on chips continues to rise.
Custom 1.0 simulation and analysis is simply not scaling; the increased complexity and smaller processes demand high-precision simulators with orders of magnitude greater speed and capacity along with simulation reduction technology. Reuse of internally developed IP is increasing across global teams - managing these dependencies is becoming a daily issue for designers.
R&D budgets are growing as the semiconductor industry undergoes major retooling for Custom 2.0 to keep pace with these demands. Custom 2.0 retooling brings a new generation of EDA custom tools designed to handle variability quickly and accurately, with a reasonable number of simulations. Device models leverage 3D process modeling. Simulators are improving in performance and capacity by one to two orders of magnitude and enabling new types of simulation that were heretofore impossible. EDA design, verification, design management, and bug tracking tools are being bound together to provide the deep dependency management required for true IP reuse.
These four key elements combined deliver Custom 2.0.
The time has come to re-architect both the environment and the simulators to meet the challenges confronting custom design today. The semiconductor industry is now facing a major retooling for “Custom 2.0” for 2013 and beyond.
Custom 2.0 retooling - drivers and outlook
The fierce competition to supply low-power, low-cost, gigahertz frequencies consumer devices is driving a move to sub-28 nm processes. All this is coupled with the need for a fast yield ramp to volume. However, while transistors are shrinking, atoms aren’t. Just a few out-of-place atoms can cause severe variability in a device, which translates into severe variability in analog/mixed-signal (AMS) and memory circuits, ultimately affecting the whole chip’s power, performance, and yield. The complexity is further exacerbated by 3D transistors.
Meeting the power, performance and area demands requires a step function change. SoCs need the latest process generations at 28nm, 20nm, and below. Somehow, the SoCs must deal with variability and all the other challenges wrought by the smaller nodes, as the percentage of embedded memory and analog on chips continues to rise.
Custom 1.0 simulation and analysis is simply not scaling; the increased complexity and smaller processes demand high-precision simulators with orders of magnitude greater speed and capacity along with simulation reduction technology. Reuse of internally developed IP is increasing across global teams - managing these dependencies is becoming a daily issue for designers.
R&D budgets are growing as the semiconductor industry undergoes major retooling for Custom 2.0 to keep pace with these demands. Custom 2.0 retooling brings a new generation of EDA custom tools designed to handle variability quickly and accurately, with a reasonable number of simulations. Device models leverage 3D process modeling. Simulators are improving in performance and capacity by one to two orders of magnitude and enabling new types of simulation that were heretofore impossible. EDA design, verification, design management, and bug tracking tools are being bound together to provide the deep dependency management required for true IP reuse.
These four key elements combined deliver Custom 2.0.
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