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Moore’s Law seen hitting big bump at 14 nm
Zvi Or-Bach
1/11/2013 2:15 PM EST
A recent EE Times article covering IMEC's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase – and still carry a hefty cost premium – due to the lack of next-generation lithography." Van den Hove provided the following slide photo as an illustration:
Yet, in another EE Times article about Intel’s 22nm IEDM presentation, EE Times quotes Mark Bohr of Intel as saying: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate," The article also quotes Bohr as saying "The increase for 14-nm wafers at Intel is nowhere near that. Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14nm."
So who is right between those two giants?
Could it be that both of them are?
In a recent blog titled Is the Cost Reduction Associated with Scaling Over? we presented charts clearly supporting Luc van den Hove's (IMEC's CEO) position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies? ).
Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.
GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, STMicro in the Fully Depleted Transistors Technology Symposium (11 December 2012) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in line with the cost roadmap of the non-Intel foundries!
Intel might indeed be different -- something did cause Intel to take what seems like an extreme measure, when it recently decided to invest $4.1B in ASML (Click Here for more details).
If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say: "However . .. we don’t intend to be in the general-purpose foundry business … [and] I don’t think the [foundry] volumes ever will be huge [for Intel]” (Click Here to see this article).
If Mark Bohr is right, then with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO, its Board should consider this as a major criterion for who should lead Intel into the future.
Finally, it is clear that dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Based on this, perhaps both Intel and non-Intel fabs should start development of Monolithic 3D IC Technology ;-)
About the author
Zvi Or-Bach is the founder of MonolithIC 3D Inc., a Finalist of the “Best of Semicon West 2011” for its monolithic 3D-IC breakthrough. Zvi was also a finalist of the EE Times 2011 and 2012 Innovator of the Year Award for his pioneering work on Monolithic 3D-ICs. Zvi can be contacted at zvi@monolithic3d.com
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peralta_mike
1/14/2013 12:21 PM EST
Ever since 1985 I have been hearing that Moore's law is about to plateau. But time and time again in one way or another the trend keeps persisting.
- Mike Peralta
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PV-Geek
1/14/2013 5:10 PM EST
The main reason that the 14nm costs are not significantly higher than the 20nm costs is that the 14nm process is not a linear shrink of the 20nm process. It is essentially a 20nm process with a 14nm FinFET transistor. So all the back end multi-patterning costs are identical to 20nm. You will see the cost curve go back on the projected track at 10nm when triple patterning and SADP start needing to be used.
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Or_Bach
1/14/2013 6:14 PM EST
The NV memory vendors has already embrace monolithic 3D as their path to keep Moore's Law (which is about cost and number of transistors and not about dimension. The logic vendors should adapt the 3D path as in addition to provides a better cost it provides far lower power. On chip interconnect is now domination logic IC power and monolithic 3D is the only practical path to increase complexity without increasing power.
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resistion
1/15/2013 9:53 PM EST
The 3D-NVM doesn't stack planes of transistors on top of one another. That approach has been abandoned by them.
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Or_Bach
1/15/2013 11:59 AM EST
Technology always come with challenges that need to be engineered. And monolithic 3D will introduce its own engineering challenges. As to the heat removal we did present in IEDM 2012 joint paper with Stanford presenting the strategy to overcome the heat removal challenge as been presented in our recent Blog http://www.monolithic3d.com/2/post/2012/12/can-heat-be-removed-from-3d-ic-stacks.html.
The more important aspect is the total power which is becoming the important limiting factor. In that respect monolithic 3D is becoming the best path to overcome this limit as on chip interconnect is now dominating ~80% of the device power as presented in this IEDM
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resistion
1/15/2013 9:48 PM EST
I think the simulation doesn't address the multi-level case, where you have heat sources sandwiched between heat sources. That is definitely a no-win situation.
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resistion
1/15/2013 9:52 PM EST
As you pointed out, there is a difference between foundries and Intel perspectives. As I pointed out, but you deleted, the difference is sensitivity to mask cost/product volume. A few more masks may be more tolerable if the volume is higher. But if there are respins of product, certainly mask cost burden is a bigger issue. E-beam maskless was proposed to completely eliminate the sensitivity, but perhaps more efficient multipatterning will arrive sooner.
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de_la_rosa
1/25/2013 3:46 PM EST
Rumors are that EUV cannot expose less than 30 nm and still have serious source issues.
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