A recent EE Times article
covering IMEC's Luc van den Hove keynote talk at IEDM 2012 reports: "Chips made at the 14-nm process node may deliver as little as half the typical 30 percent performance increase – and still carry a hefty cost premium – due to the lack of next-generation lithography."
Van den Hove provided the following slide photo as an illustration:
Yet, in another EE Times article
about Intel’s 22nm IEDM presentation, EE Times quotes Mark Bohr of Intel as saying: "Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate,"
The article also quotes Bohr as saying "The increase for 14-nm wafers at Intel is nowhere near that. Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14nm."
So who is right between those two giants?
Could it be that both of them are?
In a recent blog titled Is the Cost Reduction Associated with Scaling Over?
we presented charts clearly supporting Luc van den Hove's (IMEC's CEO) position. The following slide from an IBM presentation includes an NVidia chart (which we also discussed in another blog, Is NVIDIA in a Panic?
If so, what about AMD? Other fabless companies? ).
Accordingly, it would seem that TSMC wafer costs are in line with Luc and so is the case with IBM.
GlobalFoundries, in its recent 14nm announcement, disclosed that the back-end will be unchanged from 20nm. This suggests a similar die size and respective increase in per-transistor cost. Further, STMicro in the Fully Depleted Transistors Technology Symposium (11 December 2012) also acknowledged that their 14nm node will have a 20nm node metal pitch and, just like GlobalFoundries, a similar die size and increase in per-transistor cost.
In other words, it seems that the Luc van den Hove keynote is in line with the cost roadmap of the non-Intel foundries!
Intel might indeed be different -- something did cause Intel to take what seems like an extreme measure, when it recently decided to invest $4.1B in ASML (Click Here
for more details).
If, however, Mark Bohr has not been misled by the Intel accounting department, and the Intel process is still providing a nice cost reduction at every node of scaling, then clearly Intel has a true competitive edge relative to all other foundries. I have no doubts that Intel has filed enough patents to protect its unique process advantage, but then I wonder why did Mark say: "However . .. we don’t intend to be in the general-purpose foundry business … [and] I don’t think the [foundry] volumes ever will be huge [for Intel]”
to see this article).
If Mark Bohr is right, then with such a competitive edge Intel should aggressively expand its foundry business, which would achieve both a great profit margin and rapid business growth. Now that Intel is looking for a new CEO, its Board should consider this as a major criterion for who should lead Intel into the future.
Finally, it is clear that dimensional scaling (and its cost reducing benefits) is not what it used to be, and the market appetite for cheaper-faster-better consumer-oriented products grows stronger. Based on this, perhaps both Intel and non-Intel fabs should start development of Monolithic 3D IC Technology
;-)About the author
Zvi Or-Bach is the founder of MonolithIC 3D Inc.
, a Finalist of the “Best of Semicon West 2011” for its monolithic 3D-IC breakthrough. Zvi was also a finalist of the EE Times 2011 and 2012 Innovator of the Year Award for his pioneering work on Monolithic 3D-ICs. Zvi can be contacted at firstname.lastname@example.org
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