Cadence and Imec introduce 3D IC Memory on logic DFT

One of the predictions made by many people for 2013, was the growth in adoption of 3D chip technologies. We have already seen it for FPGA assemblies and has been in production use for memories for some time, but that does not mean to say that there are not technical hurdles that still have to be overcome. So, we should expect to see many announcements this year about new tools and methodologies to enable the design, verification, fabrication and test of these chips.

Today, one of those emerged with Cadence and Imec talking about a test technology for 3D-IC Memory on Logic – a technology essential for bringing processors and large amounts of memory together, and enabled by standards such as Wide I/O. The DFT solution tests the logic-memory interconnects in DRAM-on-logic stacks. Recently, JEDEC has released a standard (JESD-229) for stackable Wide-I/O mobile dynamic random access memories (DRAMs) specifying the logic-memory interface. Unlike many previous DRAMs, the standard contains boundary scan features to facilitate interconnect testing.

Imec and Cadence now present a design-for-test (DFT) architecture and corresponding automatic test pattern generation (ATPG) approach. It is an extension of their previously announced logic-on-logic 3D DFT architecture and it supports post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it. The solution includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAMs) of the 3D test architecture. The automated design for test solution has been validated on an industrial test chip.

The design of the test chip is an interposer-based 3D stacked IC which includes a silicon interposer base die, a 94mm² logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The validation results show that the silicon area of the additional DFT wrapper is negligible compared to the total logic die size (<0.03%). Moreover, the test pattern generation was efficient according to their press release (tens of patterns, generated in only a few seconds) and effective (100% coverage of the targeted faults).
Brian Bailey – keeping you covered

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