Agilent and SiSoft team to bring jitter to IBIS

Agilent Technologies and Signal Integrity Software (SiSoft) have released guidelines that enable system designers to use advanced jitter and broadband analog capabilities when modeling high-speed serial devices. The new modeling guidelines are based on proposed enhancements to the IBIS Algorithmic Modeling Interface (116-118 and 123.5), which are expected to be included in the specification’s next version. Both SiSoft and Agilent support the modeling techniques in the new guidelines in advance of full standardization.

Until now, IBIS-AMI models used to design and optimize high-speed serial links have lacked comprehensive jitter-modeling parameters and were limited to simple, first-order models of transmitter output drivers and receiver input-termination behavior. Including better parameters and more advanced modeling techniques in IBIS was first proposed in 2010, and the necessary extensions are expected to be approved in 2013. The new guidelines from SiSoft and Agilent enable users to create models that include techniques the two companies developed together to support design projects for mutual semiconductor and systems design customers.  

Agilent and SiSoft worked with semiconductor suppliers to upgrade their models using the new guidelines and tested the models for portability and consistency of results. An illustration of the excellent correlation achieved between the simulators is available at here.

The two companies are also working with the IBIS Open Forum to incorporate the new techniques into a future version of the IBIS specification. Doing so will further increase the accuracy, interoperability and portability of IBIS-AMI models.

Brian Bailey – keeping you covered

---

If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).

Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).