A unique EDA company: Verific

2/12/2013 8:01 AM EST

There are many unique companies in our industry, but perhaps none as unique as Verific. This company is an EDA company whose customers are EDA companies as well as end user companies who are interested in creating tools for themselves. Verific is a company that has been seeing change recently in that they see a resurgence of companies developing tools internally. In my predictions articles for 2012, Michiel Ligthart - president and COO of Verific stated “Semiconductor IP management and integration within a design flow has become more and more prevalent. As semiconductor companies cannot find off the shelf tools that fit their needs, they will develop these tools themselves. The trend will continue through 2013.”

Back in June of last year, I spoke to Rob Dekker, Verific’s CTO. We started off by speaking about the formation of the company.

Rob worked at Exemplar an early logic synthesis company that was eventually acquired by Mentor. He built their front-end parsers which was then VHDL and later Verilog. He noted the difficulty of learning a language well enough to build the parser and provide helpful information back to the user and he reasoned that everyone would need one of these. That created the seed idea for the company, one where he would provide the bones of the tool and allow the EDA company to focus on their core competence, being it logic synthesis, formal verification or whatever. While still building the company, Rob wanted to use the product himself to build an equivalence checker, and sell it cheap enough such that everyone would have one on their desks. But then he was approached by a company that wanted to do exactly the same thing, and so Rob decided that he had to either be an EDA company or a supplier to them but not both.

Of course, this also makes it much easier for chip designers or their company to create custom EDA tools. In the past, many of them used Perl scripts but designs are getting so big and complex and in many cases the companies have very specific needs that cannot be addressed by the general purpose EDA tools. I asked specifically about SystemVerilog. Rob replied:

Verilog by itself is kind of a messy format, or language, to start with. But then they built this immense amount of functionality on top of it using SystemVerilog, and that, really for us, is like a mixed blessing because if you’re building parsers for SystemVerilog, or check elaborators and so on, it’s extremely difficult and messy. The LRM is not really that rigid, it’s more like a set of guidelines and it explains the obvious but it ignores all the validity cases. Whereas in VHDL it is very structured and very clear and cleanly, clearly defined what should happen. So it’s almost easy to build a correct parser and elaborators for VHDL, but for Verilog or SystemVerilog, it’s much messier. So, SystemVerilog became so complex that it’s a mixed blessing because it’s really hard to do it right and to get all the functionality somewhat consistent with what simulators do and how they interpreted the LRM.

One of the great aspects of Verific is that often get to work with the very early stage startups in our industry – often long before they have anything to announce. Often, the first time I hear about a new startup is when there is a press release from Verific about a new client. I asked Rob about working with these companies. He had a very interesting response: