EDA/IP weekly roundup – February 20th 2013

2/20/2013 11:23 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

NanGate has announced a strategic collaboration with its EDA partner Sagantec to provide a complete automated solution for standard cell library creation at the most advanced technologies. NanGate will OEM Sagantec’s 2D dynamic compaction technology and integrate it within NanGate Library Creator™ platform. The integration will provide 14nm standard cell layout creation and validation tools. NanGate and Sagantec’s technologies complement each other and jointly enable users to produce sign-off quality DRC clean layouts in sub-22nm geometries.

Agilent has announced SystemVue 2013.01 that provides new application support for system-level architects, digital signal-processing modelers, and test-and-measurement verifiers who are designing next-generation MIMO radar systems and wireless/4G infrastructure. The new release enables users to make critical decisions about RF and DSP architecture more effectively by bringing real-world modeling, standards-based validation and links to high-performance test equipment into the R&D environment.

Breker Verification Systems has unveiled an enhanced graphical user interface (GUI) for TrekSoC™, software that automatically generates self-verifying and synchronized C test cases to run on an SoC's multiple heterogeneous embedded processors for faster and more thorough verification. TrekSoC produces multiple streams of real-world user scenarios and schedules the steps so that they cross threads and processors. Since these intertwined test cases are hard to follow, the new GUI features show clearly how the streams are scheduled across threads and how each is making progress in simulation. The GUI is part of TrekBox, the module of TrekSoC responsible for coordinating C test cases with activity in the testbench.

Mentor Graphics has announced that NXP Semiconductors has become part of the Mentor® Embedded Nucleus® Innovate Program. Participants in the Nucleus Innovate program now have access to board support packages for NXP Semiconductor microcontroller devices. The Nucleus Innovate Program targets businesses with less than $1M in annual revenue in order to help them kick-start their embedded development projects. Qualified companies can accelerate their embedded system development with software provided at no cost, including the Nucleus® Real Time Operating System (RTOS), the popular Sourcery™ CodeBench GNU toolchain, and now, 32-bit RISC ARM-based board support packages (BSP) for NXP’s LPC family of microcontrollers.

Sensory has released TrulyHandsfree™ Voice Control 3.0 with the ability for end users to create their own custom voice triggers and biometric passphrases that identify who they are and unlock features, permit access, or call up customized settings. The TrulyHandsfree trigger is a low power, high accuracy, wake-up word technology that listens for a special “wake up” phrase.

CEVA and Sensory have partnered to offer a voice recognition solution based on the CEVA-TeakLite-4 DSP and Sensory’s TrulyHandsfree™ always on voice activation technology. The solution includes Sensory’s Low Power Speech Detector technology, which reduces power consumption for always listening devices, and marks the first time this technology has been implemented on a DSP core.

EMA Design Automation has announced a new release of its static timing analysis tool, TimingDesigner 9.3, making the customization of diagrams and documentation easier and users more productive. A WYSIWYG editor has been added so users can quickly take what they see on the screen to create documentation.

ARM and STMicroelectronics have announced availability of the first ever Embedded Coder support, with MATLAB and Simulink, for ARM® Cortex™-M processor-based systems. The joint project enables software developers to create their algorithms in MATLAB and Simulink and then target, integrate, debug and test those models in a Processor In the Loop (PIL) simulation. The generated C code from Embedded Coder runs on an STM32 Evaluation Board and the debugger of the Keil™ Microcontroller Development Kit (MDK-ARM™) interfaces directly with Simulink, further simplifying the code integration.

CEA-Leti will coordinate a four-year project aimed at building a European-based supply chain in silicon photonics and speeding industrialization of the technology. The PLAT4M (Photonic Libraries And Technology for Manufacturing) project will focus on bringing the existing silicon photonics research platform to a level that enables seamless transition to industry, suitable for different application fields and levels of production volume. PLAT4M is funded by a European Commission grant of 10.2 million euros.

Mentor Graphics has a new release of the Questa® functional verification platform. This new release (10.2) provides performance improvements across the entire spectrum of engines and solutions, unified debug, verification management and analysis capabilities, and superior support of the latest methodology and language standards. This completes Mentor’s support for VHDL-2008 and adds support for the recently ratified SystemVerilog/1800-2012 including enhanced cover group specifications and generic interconnect. The Questa Platform extends its support of UPF to enable a system-level, low-power verification methodology, and delivers native support for the newly ratified Accellera UCIS (Unified Coverage Interoperability Standard).

GLOBALFOUNDRIES has enhanced the foundry’s 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform – 55nm LPe 1V – with qualified, next-generation memory and logic IP solutions from ARM. The 55nm LPe 1V is an enhanced process node to support ARM’s 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.