EDA/IP weekly roundup – February 27th 2013

2/27/2013 11:05 AM EST

This is a roundup of news or activities in the past few days that may be of interest to people.

Synopsys posted first quarter results and is raising annual EPS guidance to solid double-digit growth. The company also posted in GAAP net income, up 23 percent on a year-over-year basis from $56.7 million to $ 69.9 million. Revenue for the first quarter of fiscal 2013 was $475.1 million, compared to $425.5 million for the first quarter of fiscal 2012, an increase of 11.7 percent. GAAP net income for the first quarter of fiscal 2013 was $69.9 million, or $0.45 per share compared to $56.7 million, or $0.39 per share, for the first quarter of fiscal 2012.

Blue Pearl Software is shipping Release 6.2 of its Blue Pearl Software Suite, for Windows and Linux operating systems. The new version includes enhancements that improve and further accelerates FPGA design verification, including one of its biggest design challenges – chip-level clock domain crossing analysis. This version has analysis using a Grey Cell methodology and enhanced multi-cycle path analysis.

Mentor Graphics has expanded its automotive business unit by purchasing certain assets from MontaVista, LLC. Once integration is complete, the Mentor Graphics® automotive infotainment solution will feature the combined capabilities of the MontaVista Automotive Technology Platform (ATP) and the Mentor® Embedded Infotainment Base Platform and will be paired with sophisticated development tools including Sourcery™ CodeBench and Sourcery Analyzer.

After 1.5 years of working-group effort, the Multicore Association has announced the availability of its Multicore Task Management Application Program Interface (MTAPI) that supports the coordination of tasks on embedded parallel systems. To fully utilize homogeneous and/or heterogeneous multicore processors or systems-on-chip (SoCs), a programmer must develop software that splits a program into tasks that can be executed concurrently on different processor cores. The MTAPI specification eliminates obstacles associated with course grained solutions of today by providing an API allowing programmers to develop parallel embedded software with familiar programming processes. MTAPI features include runtime scheduling and mapping of tasks to processor cores.

Symtavision has launched SymTA/S 3.3, a major new version of its system-level tool suite for planning, optimizing and verifying embedded real-time systems. SymTA/S 3.3 features significant new timing analyses including support for FlexRay System Distribution, the new CAN-FD standard, Buffer Fill Level analysis for COM and Gateways, as well as enhanced Gantt chart customization. Major improvements to the design features of SymTA/S 3.3 include a new Customizable Wizard Framework and improved drag-and-drop functionality providing resolution of dependencies. At the same time, Symtavision has announced TraceAnalyzer 3.3, a new version of its solution for visualizing and analyzing timing data from both measurements and simulations which integrates with SymTA/S.

Accellera Systems Initiative has announced they have once again partnered with the IEEE Standards Association (IEEE-SA) to deliver an electronic design and verification standard to engineers and chip designers worldwide. The revised version of the IEEE 1800™ "Standard SystemVerilog—Unified Hardware Design, Specification, and Verification Language Reference Manual” is now available through the IEEE Get Program, which grants public access to view and download select IEEE standards at no charge.

Agilent Technologies has launched the Agilent EEsof EDA Student License Program, designed to provide access to Agilent EEsof EDA software on students’ personal computers. With the license, students no longer have to use university lab computers or log in to a university system to access Agilent EEsof software via Agilent EEsof license servers. Instead, students can now access Agilent EEsof software anyplace, anytime on their own computers. Agilent EEsof software available through the licensing program includes Advanced Design System (ADS), Electromagnetic Professional (EMPro), Genesys and SystemVue.

A new e-book from ASSET® InterTech takes a look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards. It is available on the ASSET web site http://www.asset-intertech.com/Products/Processor-Controlled-Test/PCT-Software/Cache-as-RAM-for-board-bring-up-of-non-boothing-ci

KLA-Tencor has announced the SpectraShapeTM 9000 optical critical dimension (CD) metrology system and BDR300TM backside defect inspection and review module. The SpectraShape 9000 is a new metrology system capable of monitoring the shapes of three-dimensional transistors, memory cells and other key structures that enable high-performance memory and microprocessor chips. The BDR300 inspects and reviews the back side of the wafer for defects that can cause patterning problems on the wafer’s front side. The two new systems are designed to enable volume production of integrated circuits at sub-20nm design rules.

OneSpin Solutions and Oasys Design Systems have signed an original equipment manufacturer (OEM) agreement. Under terms of the agreement, OneSpin is licensing a portion of its OneSpin 360 EC technology, automated functional equivalence checking software, to Oasys to integrate with its RealTime Designer physical RTL synthesis software. OneSpin 360 EC-ASIC is being used for synthesis verification, comparing two representations of the same design before and after synthesis to ensure functional equivalence.

Mentor Graphics has announced availability of the Kronos™ Cell Characterization and Analysis platform. The Kronos platform produces performance models for standard cells, I/Os, and complex cells. Without correctly characterized libraries, an entire design project may be at risk, and designing at the wrong environmental corner or not taking advantage of a special operating voltage may lead to slower, larger designs that waste power or take longer to close on timing.