It is time to take SoC verification out of the lab

3/6/2013 8:13 AM EST

Benefiting from more than a decade of research into co-modeling, Mentor Graphics was able to announce, in 2012, an approach that would end the reliance on external hardware devices running models of your target peripherals and instead allow you to put the emulator in your general datacenter and treat it as just another computing resource.

This new emulation approach allows designers to load their target protocol on the emulator alongside their design and drive the software side of the test process from a PC where the real target OS, drivers, and applications run safely inside a virtual machine.

This virtual lab solution is better suited for SoC verification than other approaches when the hardware and software are in the early stages of development and subject to frequent changes. For multi-million gate designs with embedded processors, multiple peripherals, and complex software tests, virtual labs offer a major step up in flexibility of use and productivity.

Functionally, virtual labs are the same as ICE, but more of the process happens in software. It’s controlled from a PC or workstation, the same hardware-accurate models used in ICE solutions are provided, and the engineer uses properly pre-validated IP. Protocol RTL models, software stacks, and applications are simply downloaded onto the emulator, which powers the SoC verification process. Like ICE, the virtual lab approach gives software engineers access to the hardware design while still in RTL, but does it flexibly and without the need for multiple setups and emulator downtime.

For hardware engineers, moving the emulator out of the lab into the datacenter puts an end to downtime caused by cable dislodgement, pin breakage, lack of available pins, or overnight waits for remote lab staff to swap cables between external hardware targets. With virtual lab emulation, engineers no longer have to depend on custom target boards to run tests.

For software engineers, it’s a more stable, resilient environment running the real target OS in a virtual machine. For example, if the code addresses a piece of memory that isn’t yet in place, there will not be a hardware crash; the PC keeps working and it’s just the virtual machine that gets rebooted.

ROI increases along with access to the emulator. In a virtual lab environment, the emulator is treated like a server available across multiple teams, projects, and geographies. It is no longer an expensive machine that’s available only to a privileged few. The goal is to enable flexible, always-on access to emulation for all of the software, hardware, and integration engineers who are working on all of an organization’s projects at the same time.

The rise in ROI, quality, and productivity gained from concurrent engineering has been a long time coming. By taking SoC verification out of the lab, virtual lab emulation creates a verification environment in which these benefits have finally arrived.

About the author

Richard Pugh has over 25 years of experience in electronic design automation, working in IP, ASIC, and SoC verification with positions in application engineering, product marketing, and business development at ViewLogic, Synopsys, and Mentor Graphics. He is currently the Product Marketing Manager for Mentor’s Emulation Division. Richard holds an MSc in Computer Science and Electronics from University College London and an MBA from Macquarie Graduate School of Management, Sydney.