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Tech Beat: Nano-structures promise power-sipping PCM
Kristin Lewotsky
3/19/2013 8:41 AM EDT
Adding a layer of nanostructured material to a phase-change memory (PCM) cell block can reduce the write current by a factor of four, say researchers from the Korea Advanced Institute of Science and Technology (KAIST). PCM is not only a contestant in the next-generation RAM derby, it shows promise for non-volatile storage applications, offering significantly better write speeds than spinning-disc media and even NAND flash. The problem is that it also requires fairly high write currents, limiting its usefulness in portable designs. Arrays of self-assembled silicon-oxide (SiOx) dots mask off some of the area of the contact pads, something like the pepperoni on a pizza, significantly cutting power demand for the technology (see figure 1).
In PCM, lithographically patterned arrays of electrodes heat the phase-change material (typically a chalcogenide glass like germanium-antimony-tellurium (GST)) to switch it between crystalline and amorphous phases. Each electrode corresponds to a bit. The smaller the electrodes, the more dense the memory – and the smaller the amount of current required to trigger the phase change. Until now, the electrode area was driven by advances in lithographic processes. The KAIST work might just change all that.
All the rules are different at the nanoscale, where surface effects outweigh bulk material characteristics. One of the nifty aspects of nanomaterials is that at the molecular and atomic level, materials can often be coaxed into self assembling. In the case of this most recent work, the team started with silicon-containing poly(styrene-b-dimethylsiloxane) (PS-b-PDMS) block copolymers, spin casting them onto a functionalized GST substrate. Microphase separation of the blocks creates small balls of the material. These self-ordered arrays block off some of the area of the contact pads to fill factors as high as 63.6%. The greater the oxide fill factor, the smaller the contact area between the titanium nitride (TiN) electrodes and the GST film, and the smaller the pads, the lower the write current (see figure 2).
To stabilize the structure, the team used reactive ion etching in an oxygen plasma environment. Modifying the parameters of the SiOx is as simple as tweaking the molecular weight or exposing them to solvents that preferentially cause one or the other block copolymer to swell.
To assess the technology, the team applied it to a PCM device with a 500 x 500 nm2 contact area. Test showed that the power required for switching dropped from 2.1 W to 0 .1 W for the nanoscale device, a 20-fold decrease. Even better, performance from device to device was quite consistent, indicating that the process is both uniform and reproducible.
Right now, it appears that the biggest problem is the approach may result in current densities on the order of 108 A/cm2. Values that high could significantly degrade device lifetime, observes PCM researcher Ron Neale. "I think current densities at that level would be destructive and cause element separation at the TiN-GST interface," he says.
The work is admittedly in the early stages – the test devices demonstrated 200 write cycles at around 0.5 V, and 3 × 103 read cycles. One challenge will be to scale the current work so that the block copolymer balls are small enough to reduce the overall contact area without completely filling it. "The problem is in the smallest device that they simulate, the oxide balls are about 5 nm in diameter and the device is 50 nm square, so I estimate a total of only nine balls in that device," says Neale. "In the rest of the work, the physical oxide balls are 20 nm in diameter. If they went down to a 20-nm diameter aperture, they would fill it. A lot will depend on how small the balls can actually be made in a reproducible manner and be in a very small aperture."
Related articles:
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Billion-dollar business seen for MRAM, PCM
Figure 1: Depositing a nanostructured layer of SiOx dots
cuts contact area and, hence, write current for
PCM cells. (Courtesy of KAIST)
cuts contact area and, hence, write current for
PCM cells. (Courtesy of KAIST)
In PCM, lithographically patterned arrays of electrodes heat the phase-change material (typically a chalcogenide glass like germanium-antimony-tellurium (GST)) to switch it between crystalline and amorphous phases. Each electrode corresponds to a bit. The smaller the electrodes, the more dense the memory – and the smaller the amount of current required to trigger the phase change. Until now, the electrode area was driven by advances in lithographic processes. The KAIST work might just change all that.
All the rules are different at the nanoscale, where surface effects outweigh bulk material characteristics. One of the nifty aspects of nanomaterials is that at the molecular and atomic level, materials can often be coaxed into self assembling. In the case of this most recent work, the team started with silicon-containing poly(styrene-b-dimethylsiloxane) (PS-b-PDMS) block copolymers, spin casting them onto a functionalized GST substrate. Microphase separation of the blocks creates small balls of the material. These self-ordered arrays block off some of the area of the contact pads to fill factors as high as 63.6%. The greater the oxide fill factor, the smaller the contact area between the titanium nitride (TiN) electrodes and the GST film, and the smaller the pads, the lower the write current (see figure 2).
Figure 2: Increasing the SiOx fill factor cuts the write current
for the PCM cell. (Courtesy of KAIST)
for the PCM cell. (Courtesy of KAIST)
To stabilize the structure, the team used reactive ion etching in an oxygen plasma environment. Modifying the parameters of the SiOx is as simple as tweaking the molecular weight or exposing them to solvents that preferentially cause one or the other block copolymer to swell.
To assess the technology, the team applied it to a PCM device with a 500 x 500 nm2 contact area. Test showed that the power required for switching dropped from 2.1 W to 0 .1 W for the nanoscale device, a 20-fold decrease. Even better, performance from device to device was quite consistent, indicating that the process is both uniform and reproducible.
Right now, it appears that the biggest problem is the approach may result in current densities on the order of 108 A/cm2. Values that high could significantly degrade device lifetime, observes PCM researcher Ron Neale. "I think current densities at that level would be destructive and cause element separation at the TiN-GST interface," he says.
The work is admittedly in the early stages – the test devices demonstrated 200 write cycles at around 0.5 V, and 3 × 103 read cycles. One challenge will be to scale the current work so that the block copolymer balls are small enough to reduce the overall contact area without completely filling it. "The problem is in the smallest device that they simulate, the oxide balls are about 5 nm in diameter and the device is 50 nm square, so I estimate a total of only nine balls in that device," says Neale. "In the rest of the work, the physical oxide balls are 20 nm in diameter. If they went down to a 20-nm diameter aperture, they would fill it. A lot will depend on how small the balls can actually be made in a reproducible manner and be in a very small aperture."
Related articles:
Tech Beat: Codewords cut PCM energy needs
PCM Progress Report No. 7: A view of Samsung's 8-Gb array
Billion-dollar business seen for MRAM, PCM
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R G.Neale
3/20/2013 9:23 AM EDT
A correction and an apology. My quote of current densities of the order 10E8 amps/sq-cm reproduced above was based on my estimate for a sub 20nm device and the reading of a less than clear version of the original paper. I have been in contact with the authors who have drawn my attention to the supplementary information provided with their paper.
From their simulation of a 50 x 50 nm device the current density without the oxide balls is 1.8 x 10E7 A/sq-cm; which is in good agreement with similar sized devices reported elsewhere. More importantly, and again from their simulation, with the oxide balls covering 50% of the area between the GST-TiN heater interface the authors estimate a reset current density of 2.8 x10E6 A/sq-cm. A value that betters by about an order of magnitude any reported so far by any other PCM workers for devices of similar dimensions. Assuming those operating conditions produce reliable overall performance especially with respect to elevated temperature data retention and write/erase lifetime the KAIST paper might mark a significant step forward in PCM development.
The next, and non-trivial step, is reduction to practice with real devices and then to put PCM back into a competitive position, devices scaled to sub 20nm dimensions. For PCM the curve of reset current density J = f(dimensions) follow the general form of those for the ratio of surface area to volume. This would suggest that sub 20nm PCM devices without the oxide balls would have current densities close to 1x10E8 amps and given a similar gain reported above with the inclusion of the balls would result in a device with a reset current density of the order 1 x10E7 A/sq-cm. Much depends on the minimum possible diameter balls and the ability to reproduce very small diameter oxide balls in sub 20nm apertures. A significant challenge remains.
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green_is_now
3/21/2013 10:25 PM EDT
Why not etch away area instead or in combination with this technque?
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green_is_now
3/21/2013 10:25 PM EDT
This will also lower contact area
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resistion
3/22/2013 4:47 AM EDT
A big problem with this is reducing the contact area increases the voltage from larger contact resistance. Also, isn't it standard practice to have design one self-assembled contact hole inside the TiN contact?
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