Programmable Logic DesignLine Blog

ESL even I can understand!

Clive Maxfield

11/16/2005 4:58 PM EST

Synthesizing C/C++ is very interesting in its place, but in many cases such solutions are targeted toward certain classes of applications such as digital signal processing (DSP) algorithms that involve lots of nested loops and similar structures. That is, these solutions are often somewhat problematical with regard to more control-intensive logic (either pure control or mixed control and dataflow).

Another consideration is that it is often difficult for designers to imagine what should be changed in the C/C++ source to effect a particular desired timing, area or latency improvement in the hardware. Furthermore, small and apparently similar changes to the C/C++ source can result in radically different hardware implementations.

One innovative solution comes from the guys and gals at Bluespec, who have created an environment based on a language they call Bluespec SystemVerilog (BSV), which is like Standard SystemVerilog on steroids. In a cool new How To article, we are introduced to Bluespec's approach to working at a high-level that keeps designers in control such that they can make tightly managed architecture and micro-architecture changes safely and quickly.



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