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Gadi Dvir
I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of ...
dylan.mcgrath
@chipmonk-Yes, of course, we at EE Times are expected to keep up with buzzwords ...
Setting the record straight on the Intel-TSMC 3-D 'race'
Dylan McGrath
7/11/2011 1:29 AM EDT
What's not to love about a story that pits semiconductor process technology leaders Intel Corp. and Taiwan Semiconductor Manufacturing Co. (TSMC) against one another in a race to achieve some high-level technical goal?
Last week, a report by the Taiwan External Trade Development Council (TAITRA), a nonprofit organization promoting trade with Taiwanese firms, did just that, issuing a report that tantalizingly suggested that TSMC might beat Intel to the punch in bringing "three-dimensional chips" to market. EE Times and other news organizations quickly seized on the report and published stories based on it.
The problem, as many EE Times readers promptly pointed out, is that the report was deeply flawed and based upon a false equivalency. While Intel is preparing to later this year bring to market chips with 3-D transistors (known as tri-gate transistors by Intel), TSMC and others have been working to develop 3-D technology based on through-silicon vias (TSVs), vertical connections that pass through die to connect different layers of a chip within the same package.
While the language of the TAITRA report was not totally clear, a minimal amount of investigation quickly revealed that the report was comparing apples to oranges, setting up a "race" between Intel's delivery of tri-gate devices with TSMC's offering of chips with TSVs. The only thing that these technologies have in common, essentially, is that they are both technologies that can be described as 3-D, one of the most popular buzzwords in technology these days.
The race between Intel and TSMC imagined by the TAITRA report is not unlike musing about competition between swimmer Michael Phelps and sprinter Usain Bolt at the 2012 Olympics: two world-class competitors gunning for high-level achievements in completely different sports.
The TAITRA report cited an anonymous source within TSMC saying that TSMC's schedule for 3-D chip rollout matched that of Intel, which has said it expects its tri-gate devices to be ready for volume production by the end of the year. The report did not get into the specifics of the TSMC 3-D technology, instead using language similar to that which Intel used during the tri-gate launch in May to describe 3-D chips in general.
TSMC is developing its own 3-D transistor technology, known as FinFET, which is similar to Intel's tri-gates. But TSMC said as recently as February that it does not expect to put FinFET devices into production until 2015 or 2016. In other words, it's highly unlikely that TAITRA's anonymous TSMC source was referring to TSMC's FinFET technology being in volume production by the end of this year (which would have made it more of an apples to apples comparison).
TSMC has not provided an official production schedule for its TSV technology. In April, TSMC did not provide an update for its TSV roadmap at its annual technology symposium, as the foundry giant has done in the past. TSMC was low key about TSVs this year and said TSV development was "still in the early stages." Nevertheless, it's far more likely that TAITRA's anonymous source was referring to TSV devices being in production by the end of the year than FinFETs. The TAITRA report quoted Shang-Yi Chiang, senior vice president for R&D at TSMC, saying the company has been working closely with packaging and design software providers to commercialize the technology.
Intel, by the way, is also developing 3-D chip stacking through TSVs, as are a host of other semiconductor firms, including Samsung Electronics Co. Ltd., Elpida Memory Inc., IBM Corp., Toshiba Corp. and chip packaging provider Advanced Semiconductor Engineering Inc., among others. It's not yet known when any of these companies plan to put chips with TSVs into production. Last summer, at the International Interconnect Technology Conference, several experts agreed that the technology was some ways away from commercialization.
To sum up: TAITRA circulated a deeply flawed report that inaccurately equated two completely different technologies that have only one thing in common, the fact that they are both described as 3-D technology. Let's assume that this was an honest mistake by TAITRA, based on a fundamental lack of understanding of the technologies. (TAITRA's press agents did not immediately respond to a request for an interview about the creation of the report).
It was a mistake by EE Times (specifically, sloppy journalism by yours truly) to lend credence to the TAITRA report by publishing a story based on it. A good portion of our coverage is based on relevant reports produced by third parties. But journalistic standards demand that we kick the tires of these reports and assess their credibility, and in this case that was not done adequately.
Last week, a report by the Taiwan External Trade Development Council (TAITRA), a nonprofit organization promoting trade with Taiwanese firms, did just that, issuing a report that tantalizingly suggested that TSMC might beat Intel to the punch in bringing "three-dimensional chips" to market. EE Times and other news organizations quickly seized on the report and published stories based on it.
The problem, as many EE Times readers promptly pointed out, is that the report was deeply flawed and based upon a false equivalency. While Intel is preparing to later this year bring to market chips with 3-D transistors (known as tri-gate transistors by Intel), TSMC and others have been working to develop 3-D technology based on through-silicon vias (TSVs), vertical connections that pass through die to connect different layers of a chip within the same package.
While the language of the TAITRA report was not totally clear, a minimal amount of investigation quickly revealed that the report was comparing apples to oranges, setting up a "race" between Intel's delivery of tri-gate devices with TSMC's offering of chips with TSVs. The only thing that these technologies have in common, essentially, is that they are both technologies that can be described as 3-D, one of the most popular buzzwords in technology these days.
The race between Intel and TSMC imagined by the TAITRA report is not unlike musing about competition between swimmer Michael Phelps and sprinter Usain Bolt at the 2012 Olympics: two world-class competitors gunning for high-level achievements in completely different sports.
The TAITRA report cited an anonymous source within TSMC saying that TSMC's schedule for 3-D chip rollout matched that of Intel, which has said it expects its tri-gate devices to be ready for volume production by the end of the year. The report did not get into the specifics of the TSMC 3-D technology, instead using language similar to that which Intel used during the tri-gate launch in May to describe 3-D chips in general.
TSMC is developing its own 3-D transistor technology, known as FinFET, which is similar to Intel's tri-gates. But TSMC said as recently as February that it does not expect to put FinFET devices into production until 2015 or 2016. In other words, it's highly unlikely that TAITRA's anonymous TSMC source was referring to TSMC's FinFET technology being in volume production by the end of this year (which would have made it more of an apples to apples comparison).
TSMC has not provided an official production schedule for its TSV technology. In April, TSMC did not provide an update for its TSV roadmap at its annual technology symposium, as the foundry giant has done in the past. TSMC was low key about TSVs this year and said TSV development was "still in the early stages." Nevertheless, it's far more likely that TAITRA's anonymous source was referring to TSV devices being in production by the end of the year than FinFETs. The TAITRA report quoted Shang-Yi Chiang, senior vice president for R&D at TSMC, saying the company has been working closely with packaging and design software providers to commercialize the technology.
Intel, by the way, is also developing 3-D chip stacking through TSVs, as are a host of other semiconductor firms, including Samsung Electronics Co. Ltd., Elpida Memory Inc., IBM Corp., Toshiba Corp. and chip packaging provider Advanced Semiconductor Engineering Inc., among others. It's not yet known when any of these companies plan to put chips with TSVs into production. Last summer, at the International Interconnect Technology Conference, several experts agreed that the technology was some ways away from commercialization.
To sum up: TAITRA circulated a deeply flawed report that inaccurately equated two completely different technologies that have only one thing in common, the fact that they are both described as 3-D technology. Let's assume that this was an honest mistake by TAITRA, based on a fundamental lack of understanding of the technologies. (TAITRA's press agents did not immediately respond to a request for an interview about the creation of the report).
It was a mistake by EE Times (specifically, sloppy journalism by yours truly) to lend credence to the TAITRA report by publishing a story based on it. A good portion of our coverage is based on relevant reports produced by third parties. But journalistic standards demand that we kick the tires of these reports and assess their credibility, and in this case that was not done adequately.
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sxs537
7/11/2011 3:47 PM EDT
Thanks Dylan for coming back and clarifying the story. Not many people would offer a Mean Culpa when they make a mistake. So Kudos to you and EETimes and shame on all the other journalists who still continue to carry that story.
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sxs537
7/11/2011 3:47 PM EDT
I meant mea culpa and not "Mean Culpa" :) :)
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dylan.mcgrath
7/11/2011 4:07 PM EDT
Thanks for the comment. We're not above owning up to it when we goof, which (hopefully) is rare. But it does happen.
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Geetree
7/12/2011 10:52 PM EDT
When you say "flawed report that falsely equivocated" and later say "this was an honest mistake" these are countradictry... I think you mean 'conflated'..?? and not "equivocated"=past participle, past tense of e·quiv·o·cate
Verb: Use ambiguous language so as to conceal the truth or to avoid committing oneself. Was it sensationalism on purpose - just ignorant? or both?
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dylan.mcgrath
7/13/2011 5:11 PM EDT
I don't believe it was sensationalism on purpose. I think it was an honest mistake. The author of the report, despite talking to experts, didn't understand that these were two completely different technologies. He emailed me earlier this week to say as much and also apologize. The report treated the technologies as identical, when in reality they are quite different. But, as I said, it was an honest mistake based on a lack of understanding.
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docdivakar
7/15/2011 12:50 PM EDT
Dylan, you have adequately explained in the article for the misread -in fact, the entire article is honestly & openly admissive of the error so I don't see why additional apologies / explanations are needed.
I was one of the few skeptics that didn't believe TSMC & Intel were talking about the same 3D when I looked at the title. TSMC is obviously not in the business of developing new incarnations of FETs. Their motivation for monolithic 3D via FinFETs comes from being ready with a process for the same.
The fault lies with too many people using loosely and liberally the term "3D IC" and not recognizing the stark contrasts between various versions of it.
Sorry, we couldn't tag at the Semicon -I was drowning in non-stop ingestion of technical information! Cheers!
MP Divakar
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dylan.mcgrath
7/18/2011 5:43 PM EDT
MP- Thanks for the note. I'm also sorry that we didn't get a chance to meet face to face at the show.
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Gadi Dvir
7/18/2012 2:18 PM EDT
I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of Moore's law - reduction of the area of the transistor and the cells used for creating microelectornics devices will reduce the cost of the manufactring. There are side benfits of potential increase in speed and reduced energy per switching action that can be capture through this effort. Moore's law will end due to laws of physiscs ( how small can switching device get). As part of getting closer to the the physics limit - there is need for more vertical structures to provide the finctionality needed to reduce space. In the previous 15-20 years it was by adding metal layers; Then came incorporation of new materils into the stack that required more processing (layers = vertical additions). Now we are in Tri Gate and TSVs that again - allow to build "High Risers"in different ways ( condos's in the bottom floor, or simply put one strucutre on top of the other). However - we get to the point that the saving will be offset by the ocst of processing and then when Moore's law as we enjoyed it for the last 4 decades, stops- probably a bit before the absolute physical limitaion.
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resistion
7/13/2011 11:27 AM EDT
An unfortunate marketing embarrassment for Taiwan.
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michigan
7/14/2011 12:39 AM EDT
I would like to lay out some of the facts about Intel-TSMS FinFETs. TSMC recently published two papers on FinFET CMOS in IEDM, December, 2010, one for high performance 22/20nm and the other for low power 32/28 SoC technology. TSMC reported in both cases a comprehensive data on process, device, SRAM and reliability including their statistical data meaning ready for volume production. TSMC, however, has not announced when it will be manufactured. Intel has not published its FinFET data except mostly news release for public consumption, and not for technical community. This is in contradiction to Intel’s past practices. Intel published new technology nodes such as 65nm, 45nm, and 32nm either in IEDM or in VLSI symposium before production or at the same time except its 22nm FinFET technology. Why? So, we can not compare technically or to see how TSMC chip matches that of Intel because no comparative technical data is provided by Intel. Intel has announced volume production around the end of 2011. It is very unfortunate to claim that TAITRA is not aware of TSMC’s FinFET technology progress, and even can not distinguish FinFETs from TSVs. My question to Dylan McGrath and those posted here is whether they have read TSMC papers on FinFETs published in IEDM as I referred above. They should, and see what technical information provided by TSMC compared with Intel. TSMC is a foundry company. As such it dose not compete directly with Intel. TSMC is ahead of its rivals such as IBM alliances and GlobalFoundries at 28nm that is in volume production this year. ARM has joined TSMC recently leaving IBM alliances for development of ARM processor at 28nm and FinFETs in near future. Therefore, TSMC dose not have to manufacture its FinFETs this year, but will be ready when in need. TSMC will be a formidable competitor for development of FinFETs beyond 22nm such as 14/12nm and 8/6nm in 2016 time period.
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nicolas.mokhoff
7/15/2011 11:04 AM EDT
michigan: It would be good to point out the IEDM 2010 technical paper numbers you refer to. Perhaps you would like to expand your points in an Opinion piece?
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michigan
7/17/2011 6:23 PM EDT
I am glad that you asked the paper numbers because initially I included the paper titles and paper numbers in my post, but deleted because of over the space limit. The title of the first paper is “High Performance 22/20nm FinFET CMOS Devices with Advanced High K/Metal Gate Scheme”, Page # 27.1.1. The second paper title is “A low Operating Power FinFET Transistor Modules Featuring Gate Stack and Strain Engineering for 32/28nm SoC Technology”, Page # 34.1.1. There is no conference digest, but you can obtain IEDM CD by contacting Phyllis Mahoney, E-mail: phyllism@widerkehr.com . Intel made a public announcement of its FinFETs and high volume manufacturing around the end of the 4th quarter, 2011. Intel also said it will provide no more technical details at the question and answer session. But that announcement came more than four month after TSMC papers were published. Under these circumstances TSMC reported that TSMC may beat Intel to 3-D chips. Beat here means in my interpretation that TSMC can demonstrate manufacturability of the FinFET chips with reasonable yields, performance and reliability, but not high Volume manufacturing. TSMC may do that. I am also very confident that Intel will meet the high Volume manufacturing schedule this year as reported. If you want to know more about FinFE and its device physics, please read my post in SuVolta’s new transistor option for 20nm – EDN, June 22, 2011. Sang
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iniewski
7/17/2011 10:52 PM EDT
thank you for the info @michigan, I am editing a book on nanoelectronics, would you be interested in contributing a chapter? kris.iniewski@gmail.com
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resistion
7/18/2011 1:06 AM EDT
I think your definition hinges too much on one-time results for publication. In this case universities beat companies almost all the time. You need sustained manufacturing yield. This is not published, but results in products which may be reverse engineered.
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michigan
7/21/2011 12:45 PM EDT
The papers presented by TSMC represent a typical format used to assess device functionality and advancement of a new technology node such as 22nm. The format is used by companies as seen from the previous technology nodes such as 45nm and 32/28nm (see old IEDM and VLSI symposium issues). The data are generated on test chip and wafer. The figures from 1-17 as shown in the first TSMC paper are generated from such test chips on several hundreds of data points, but not from product modules because the product wafers are not available yet. To generate such test chip data may take several months to a year and definitely not “one-time results” as you state. I have not seen any university data similar to the figures (1- 17) at 22nm. I don’t think IEDM and VLSI are interested in production data including yield. Beside, company normally dose not publish the product yield data except to its customers. I am sure that companies like Intel, TSMC, IBM and others have already started the test chip design for 14nm to meet Moore’s Law, not for publicity.
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iniewski
7/15/2011 10:51 AM EDT
thank you Dylan for straightening this out...I could not made any sense of that report when I read it the first time, but I thought I was just too tired ;-)...Kris
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HengChun.Kao
7/18/2011 10:02 PM EDT
Thank you for all you share and comment. Can someone kindly share with me the original article by TAITRA? What I read are all EETimes reports.
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chipmonk
7/27/2011 3:04 PM EDT
Are EE Times Reporters / Editors these days expected to keep up with the latest technology or buzzwords ( e,g. the difference between 3D at the device level as compared to die level ? ). For that matter are articles from various non -technical / suspect sources ( e,g. the Taiwan websites, or for that matter AP, Reuters ) first checked for accuracy before uploading at EE Times ?
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dylan.mcgrath
7/27/2011 3:17 PM EDT
@chipmonk-Yes, of course, we at EE Times are expected to keep up with buzzwords and know the difference between various technologies. We do not upload any articles from the sources that you mention, but we do sometimes write stories based on their reports. When we do that, we reveiew them and make a determination as to their accuracy and credibility. If they don't pass that test, we don't do anything with them. That is what we should have done in the case of the Taitra report--reviewed it and then determined it was inaccurate and thus a non story. But as mentioned above, I made a mistake in this case. My apologies.
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