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resistion
It would make hell of a good sauna. ;)
peter.clarke
It is also a fraction of the total required to generate that EUV power.
Even with Intel's chips on the table, EUV still no sure bet
Dylan McGrath
7/19/2012 2:28 PM EDT
Proponents of extreme ultraviolet (EUV) lithography were understandably encouraged last week when Intel Corp. entered into a $4.1 billion equity and funding deal to help boost R&D efforts for 450-mm and EUV lithography tools.
"It's the best news I've heard in a long time," said David Brandt, senior director of euv marketing and business development at Cymer Inc., a long-time source developer for ASML and the front-runner in working with the Dutch lithography vendor to improve source power for EUV tools.
Intel already had a vested stake in making sure that EUV development remains on track to put the technology into production, even if much later than Intel had originally hoped. Intel and the rest of the thinning ranks of leading-edge chip makers have every reason to want cost-effective EUV lithography to save them from the pain and expense of extending 193-nm optical lithography to the 10-nm node and beyond. Brandt and others took Intel's willingness to put skin in the EUV game as a vote of confidence in the viability of the oft-delayed technology.
But Intel's wallet alone won't bring EUV into production. Though incremental progress on the EUV development front has been reported over the past week, there remains--as there has since the technology landed on the ITRS roadmap--work to be done. EUV is, at best, still years away from volume production and remains no slam dunk.
In a presentation at last week's Semicon West tradeshow, Franklin Kalk, chief technology officer at Toppan Photomasks Inc., said source power, mask defectivity and photoresist performance remain the three issues still facing volume production of chips using EUV. But, Kalk said, source power remains the main hurdle, as it has for some time.
Three years ago, Kalk said, mask defectivity was considered the main stumbling block for EUV, and thus the burden of Toppan and its competitors. But in the past couple of years, the failure to develop a source powerful and reliable enough to provide adequate tool throughput has taken center stage. "I'm hoping that source power gets high enough that they start complaining about the masks again."
Chip makers want EUV tools with a throughput of 100 to 150 wafers per hour to make production EUV cost effective. Some say a tool throughput of 60 to 80 wafers per hour would be a sufficient starting point. Even that type of throughput remains out of reach for now, though AMSL CEO Eric Meurice said this week that research progress indicates that EUV throughput is on pace to reach 70 wafers per hour in 2014 and 125 wafers per hour in 2016.
"It's the best news I've heard in a long time," said David Brandt, senior director of euv marketing and business development at Cymer Inc., a long-time source developer for ASML and the front-runner in working with the Dutch lithography vendor to improve source power for EUV tools.
Intel already had a vested stake in making sure that EUV development remains on track to put the technology into production, even if much later than Intel had originally hoped. Intel and the rest of the thinning ranks of leading-edge chip makers have every reason to want cost-effective EUV lithography to save them from the pain and expense of extending 193-nm optical lithography to the 10-nm node and beyond. Brandt and others took Intel's willingness to put skin in the EUV game as a vote of confidence in the viability of the oft-delayed technology.
But Intel's wallet alone won't bring EUV into production. Though incremental progress on the EUV development front has been reported over the past week, there remains--as there has since the technology landed on the ITRS roadmap--work to be done. EUV is, at best, still years away from volume production and remains no slam dunk.
In a presentation at last week's Semicon West tradeshow, Franklin Kalk, chief technology officer at Toppan Photomasks Inc., said source power, mask defectivity and photoresist performance remain the three issues still facing volume production of chips using EUV. But, Kalk said, source power remains the main hurdle, as it has for some time.
Three years ago, Kalk said, mask defectivity was considered the main stumbling block for EUV, and thus the burden of Toppan and its competitors. But in the past couple of years, the failure to develop a source powerful and reliable enough to provide adequate tool throughput has taken center stage. "I'm hoping that source power gets high enough that they start complaining about the masks again."
Chip makers want EUV tools with a throughput of 100 to 150 wafers per hour to make production EUV cost effective. Some say a tool throughput of 60 to 80 wafers per hour would be a sufficient starting point. Even that type of throughput remains out of reach for now, though AMSL CEO Eric Meurice said this week that research progress indicates that EUV throughput is on pace to reach 70 wafers per hour in 2014 and 125 wafers per hour in 2016.
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dylan.mcgrath
7/19/2012 8:55 PM EDT
Intel's pocket book and ASML's reported progress are positive developments for EUV. But after years of ups and downs and missed schedules, can we count on EUV in 2014, 2016, 2018 or ever?
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philaix
7/20/2012 3:06 AM EDT
What will be the price of a mask set for the techno addressed ?
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any1
7/20/2012 10:03 AM EDT
I doubt that we will see adoption of EUV as early as 2014. Even 2016 is not certain, but that's too far out to predict. My best guess is that EUV will happen eventually for a small group of companies that can justify the cost with high volumes, but there are other technologies now on the horizon that could supplant EUV or at least coexist with EUV for certain applications, or lower volumes where it would be difficult to amortize the cost of an EUV mask set.
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resistion
7/20/2012 12:45 PM EDT
This year Intel already raised the power requirement for EUV at 20 nm feature size (whatever node it is called) by a factor of several. Samsung knows the same issue for DRAM contacts at same size (shot noise). With this new awareness, the contingencies should be being accelerated in panic mode right now.
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askubel
7/20/2012 6:01 PM EDT
Even since the article on July 9th saying they were "in talks with ASML", I haven't heard anything more about zPlasma (http://www.eetimes.com/electronics-news/4389852/EUV-startup-in-talks-with-ASML)
They believe they can have a 200W power source integrated into production equipment within four years for $5 million. Time will tell if this is actually possible, but at the very least they have a unique approach to the source problem.
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resistion
7/20/2012 10:50 PM EDT
The trouble with any scale-up solution such as this is the EUV power is a very small fraction of the total which is dominated by heat. The thermal loading at target EUV levels has not been comprehended.
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peter.clarke
7/23/2012 10:19 AM EDT
It is also a fraction of the total required to generate that EUV power.
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resistion
7/23/2012 5:14 PM EDT
It would make hell of a good sauna. ;)
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