Memory Designline Blog
DESIGN West remembers memory
Kristin Lewotsky
3/26/2012 4:08 PM EDT
DESIGN West is under way this week in San Jose. The four-day meeting combines the Embedded Systems Conference & Exhibition with additional technical summits on a range of topics including multicore, medical design, Android, security, LED design, and sensors. Memory, of course, is a core technology for embedded design, and from the session rooms to the exhibit floor, DESIGN West features plenty of content on the topic.
On the exhibit floor, a series of workshops delivers practical tips and tutorials. DRAM might be considered a commodity but choosing the right DRAM module for your design isn’t as simple as it seems. It requires making informed tradeoffs among performance, power, and density, striving to meet system requirements while hitting the targeted price and product life numbers. In “Choosing the DRAM with Complex System Considerations,” Todd Legler of Micron Technology will help you make sense of future DRAM technologies & trends and understand how to arrive at the best choice. (Tuesday 3/27, 12 noon; Wednesday 3/28, 3:00 pm)
Although increased semiconductor capabilities offer huge rewards, a side effect of higher-performance systems is the increased probability of soft errors. Decreasing supply voltages make integrated circuits more susceptible to electromagnetic and particle radiation. As memory size in embedded systems grows to hundreds of megabytes, soft errors may exceed acceptable levels due to naturally occurring alpha particles. Meanwhile, interface speeds in excess of 1 Gb/s trigger excessive noise and jitter that can cause errors in the transmission lines to and from external memory.
In “Making SoC FPGA- Based Memory Systems More Resilient to Soft Errors Through Detection and Correction,” Matt Prather and Hans Spanjaart of Altera examine the sources and implications of soft errors and discuss ways to make embedded systems more resilient to these effects. (Tuesday 3/27, 4:30pm; Wednesday 3/28, 12:00pm)
The technical sessions feature a number of memory highlights, including:
ESC-325 Evolving Wireless Sensor Networks with Low Power Memory
Ferroelectric random access memory (FRAM), features endurance a billion times that of flash memory, along with write speeds over 1000 faster. It does not require power-intensive operations like mass erase, charge pumps, or blocked erases. In addition, FRAM enables ultra low-power applications with a reduction of up to 100 times less power consumption. This is accomplished through the unique structure, materials, and capability implemented in FRAM. Jacob Borgeson of Texas Instruments reviews the basics of FRAM, how the writes are structured, and how this leads to a very low-power solution for wireless sensor networks. Want a demonstration? He'll show how it can be implemented secure electronic building access. (Wednesday 3/28, 4:30 pm)
ESC-412 Improved Memory Throughput Using Serial NOR Flash
Today's NOR-based serial peripheral interface (SPI) memories have reached 10 to 8 MHz clock rates with a QuadIO (x4) interface to achieve a 54-MB/s sustained read throughput while remaining compatible with the original interface specified nearly 25 years ago. The legacy SPI interface and bus protocol is reaching fundamental timing limits that will complicate further increases to the SPI bus clock rate, however. Spansion’s Cliff Zitlaw describes both system-level and memory-device strategies that deal with these timing limitations, allowing higher SPI bus throughputs. (Thursday 3/29, 2:00 PM)
ME-308 What Happens When Multicore Hits the Memory Wall?
Multicore technology may have provided us with a way to boost processing power but there is a looming problem out there referred to as the memory wall. Multicore sockets from Intel, AMD, IBM, and Nvidia do not provide linear application speed-up with increasing core counts. While not all applications parallelize well, a disturbing multicore phenomenon comes down to a fundamental I/O bottleneck. Cores per die scales with Moore's Law, but interconnect to off-chip DRAM, PCI Express, Ethernet, and disk drives does not. Simply stated: multicore CPUs and GPUs are hitting the memory wall. Al Wegener of Samplify Systems reviews recent trends in supercomputing, quantified by 10%-or-less-processor utilization, that foreshadow impending multicore I/O bottlenecks. Look for him to present various architectural improvements such as map/reduce, improved DMA hardware, and flexible compression, that together can forge an assault on the multicore memory wall. (Wednesday 3/28, 3:20 pm)
If the memory wall is on your mind, keep an eye on DESIGN West coverage—Micron is expected to present roadmap information on the hybrid memory cube.
If you can’t attend the meeting, you can still stay up to date. To keep posted on the latest happenings at DESIGN West, follow the intrepid onsite team on Twitter (hashtag #designwest).
On the exhibit floor, a series of workshops delivers practical tips and tutorials. DRAM might be considered a commodity but choosing the right DRAM module for your design isn’t as simple as it seems. It requires making informed tradeoffs among performance, power, and density, striving to meet system requirements while hitting the targeted price and product life numbers. In “Choosing the DRAM with Complex System Considerations,” Todd Legler of Micron Technology will help you make sense of future DRAM technologies & trends and understand how to arrive at the best choice. (Tuesday 3/27, 12 noon; Wednesday 3/28, 3:00 pm)
Although increased semiconductor capabilities offer huge rewards, a side effect of higher-performance systems is the increased probability of soft errors. Decreasing supply voltages make integrated circuits more susceptible to electromagnetic and particle radiation. As memory size in embedded systems grows to hundreds of megabytes, soft errors may exceed acceptable levels due to naturally occurring alpha particles. Meanwhile, interface speeds in excess of 1 Gb/s trigger excessive noise and jitter that can cause errors in the transmission lines to and from external memory.
In “Making SoC FPGA- Based Memory Systems More Resilient to Soft Errors Through Detection and Correction,” Matt Prather and Hans Spanjaart of Altera examine the sources and implications of soft errors and discuss ways to make embedded systems more resilient to these effects. (Tuesday 3/27, 4:30pm; Wednesday 3/28, 12:00pm)
The technical sessions feature a number of memory highlights, including:
ESC-325 Evolving Wireless Sensor Networks with Low Power Memory
Ferroelectric random access memory (FRAM), features endurance a billion times that of flash memory, along with write speeds over 1000 faster. It does not require power-intensive operations like mass erase, charge pumps, or blocked erases. In addition, FRAM enables ultra low-power applications with a reduction of up to 100 times less power consumption. This is accomplished through the unique structure, materials, and capability implemented in FRAM. Jacob Borgeson of Texas Instruments reviews the basics of FRAM, how the writes are structured, and how this leads to a very low-power solution for wireless sensor networks. Want a demonstration? He'll show how it can be implemented secure electronic building access. (Wednesday 3/28, 4:30 pm)
ESC-412 Improved Memory Throughput Using Serial NOR Flash
Today's NOR-based serial peripheral interface (SPI) memories have reached 10 to 8 MHz clock rates with a QuadIO (x4) interface to achieve a 54-MB/s sustained read throughput while remaining compatible with the original interface specified nearly 25 years ago. The legacy SPI interface and bus protocol is reaching fundamental timing limits that will complicate further increases to the SPI bus clock rate, however. Spansion’s Cliff Zitlaw describes both system-level and memory-device strategies that deal with these timing limitations, allowing higher SPI bus throughputs. (Thursday 3/29, 2:00 PM)
ME-308 What Happens When Multicore Hits the Memory Wall?
Multicore technology may have provided us with a way to boost processing power but there is a looming problem out there referred to as the memory wall. Multicore sockets from Intel, AMD, IBM, and Nvidia do not provide linear application speed-up with increasing core counts. While not all applications parallelize well, a disturbing multicore phenomenon comes down to a fundamental I/O bottleneck. Cores per die scales with Moore's Law, but interconnect to off-chip DRAM, PCI Express, Ethernet, and disk drives does not. Simply stated: multicore CPUs and GPUs are hitting the memory wall. Al Wegener of Samplify Systems reviews recent trends in supercomputing, quantified by 10%-or-less-processor utilization, that foreshadow impending multicore I/O bottlenecks. Look for him to present various architectural improvements such as map/reduce, improved DMA hardware, and flexible compression, that together can forge an assault on the multicore memory wall. (Wednesday 3/28, 3:20 pm)
If the memory wall is on your mind, keep an eye on DESIGN West coverage—Micron is expected to present roadmap information on the hybrid memory cube.
If you can’t attend the meeting, you can still stay up to date. To keep posted on the latest happenings at DESIGN West, follow the intrepid onsite team on Twitter (hashtag #designwest).
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