New Companies exhibiting at DAC: ICScape

DAC is quickly approaching and with it we can expect to see many new companies showing their tools for the very first time. I will be publishing a list of them in the next couple of days. In this blog, I want to introduce one of those companies, a company that is not typical in many ways and one that may be a sign of things to come.

I will start with what makes ICScape somewhat untypical. The company has several products: a physically-aware timing ECO tool, TimingExplorer; ClockExplorer, which automates complex SoC clock analysis and optimization; Skipper, an IC finishing solution; and FlashLVL, a layout versus layout comparison (XOR) tool.

ClockExplorer was adopted by two strategic customers immediately after its launch in 2007. Timing Explorer, had 10 tapeouts in its first year when launched in 2009. The original venture capital came from David Tsang, co-founder and managing partner of Acorn Campus Ventures in 2005 and they are still trying to consume that money.

But the company founders had bigger ideas and did not want to consider the normal exit path for an EDA company – acquisition by one of the big three. Instead, they intend to become a global EDA player themselves and to do that, they needed additional products and additional capital.

This is where things get interesting. The US has not been a good place for VC money in the EDA industry recently, although a small amount of money has started flowing again. Instead, they looked to China and found a well-established EDA company there - Huada Empyrean Software (HES). They are subsidiary of China Electronics Corporation, China's largest electronics conglomerate with over $23B in revenue in 2011. HES had an OpenAccess-based Analog tool suite. This was right in line with ICScape’s more recent development path in which they had developed place and route technology, CTS, static timing analysis, parasitic extraction etc for digital designs. By coupling the two product lines together they hope to create a complete flow for analog, mixed-signal designs by the end of this year and have early Beta in the hands of a couple of customers today.



So, CEC provided the merged company with $28M to help cement those product goals. They are using that money to expand their R&D team which is based both here in the US and in China. 60-70% of their personnel is in R&D, with 90% of them in China. A further 15-20% of their staff are AEs. Their key architects and management is in the US.

I talked to them about the Chinese design market. They said the quality of engineers is the same in both countries, although a lot cheaper in China. They said the China semiconductor industry is growing fast, but the technology is not quite as advanced as the US. However, some companies are building very sophisticated designs already. They also said that you cannot build less capable tools for the Chinese markets because so many international companies have a presence in China and they require the same tools at all of their locations.

So, pay them a visit at DAC – Booth 1602

Steve Yang, Co-founder and President, started his career at Sun Microsystems as a Member of the Technical Staff, responsible for in-house CAD tool development and later became a circuit designer on one of the microprocessor design teams in the microprocessor division.  Afterward, Yang joined Synopsys and was responsible for clock tree synthesis research and development in the Physical Implementation Group. Yang received his BSEE from Tsinghua University (Beijing) and Ph.D. from the University of California, San Diego.


Jason Xing, Co-founder and Vice President of Engineering, has over 15 years EDA research and development experience. In 1997, Xing joined Sun Labs after receiving his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign. At Sun Labs, Xing did research on physical and logical concurrent design methodologies and shape-based routing algorithms. In 2001, Xing joined the internal CAD development team in the microprocessor division. Xing holds a Ph.D. from the University of Louisiana in Mathematics.

K.C. Chen, Vice President of R&D, previously was Co-founder, CTO and Sr. Vice President of R&D at Verplex Systems Inc., which was the industry leader in formal verification tools before being acquired by Cadence Design Systems in 2003. Before starting Verplex Systems in 1997, Chen held various engineering and management positions at Fujitsu Labs. Chen is also a General Partner of the NACSE Angel Fund, which he co-founded in 2004 with other successful entrepreneurs in Silicon Valley. Chen holds a Ph.D. and M.S. in Computer Science from the University of Illinois at Urbana-Champaign and has over 20 years experience in the EDA and software industries.


Brian Bailey – keeping you covered

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