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SIG, Panel and more at DAC
Brian Bailey
5/17/2012 10:54 AM EDT
DAC will be a busy time for me this year, including talking to lots of startup companies to hear their views and opinions about what it takes to be successful in the EDA industry. All of those will be appearing in the Entrepreneurs series. I am also moderating a couple of events this year. The first event is the PrimeTime Special Interest Group (SIG) Dinner on Monday evening that is being hosted by Synopsys. This is the 4th time they have held this event at DAC and is an opportunity for PrimeTime users and design engineers to stay connected with the latest developments in the field of Static Timing Analysis (STA). Register for this event here. Oh and by the way, there will be a team contest at the event and the winning table will all receive a Samsung Galaxy Tab.
On Tuesday, I will be the moderator the DAC panel: System Models - Does One Size Fit All?
This is at 1:30 in Room 305 and we will be discussing models that satisfy the needs of software developers, system architects, hardware developers, and verification engineers. Of course, you know I have my own views in this space and I will be asking the panelists about them. The panelists are: Stuart Swan – Cadence, Rick Higgins - Qualcomm, John Goodenough - ARM, Frederic Risacher - Research in Motion and Andrea Kroll – Tensilica.
You will also be able to catch me on the Breker booth (2501) at 2pm on Monday, 11:00am on Tuesday and 12:00 on Wednesday, where I will be giving a brief presentation on the problems and opportunities in the verification space.
I hope to see you at one of those events, or at one of the many other great sessions and panels at the conference.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
On Tuesday, I will be the moderator the DAC panel: System Models - Does One Size Fit All?
This is at 1:30 in Room 305 and we will be discussing models that satisfy the needs of software developers, system architects, hardware developers, and verification engineers. Of course, you know I have my own views in this space and I will be asking the panelists about them. The panelists are: Stuart Swan – Cadence, Rick Higgins - Qualcomm, John Goodenough - ARM, Frederic Risacher - Research in Motion and Andrea Kroll – Tensilica.
You will also be able to catch me on the Breker booth (2501) at 2pm on Monday, 11:00am on Tuesday and 12:00 on Wednesday, where I will be giving a brief presentation on the problems and opportunities in the verification space.
I hope to see you at one of those events, or at one of the many other great sessions and panels at the conference.
Brian Bailey – keeping you covered
If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you).
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