Technologies, developers of the industry standard for integrated circuit
(IC) soft error analysis and prevention will present the latest
functionalities and performance of TFIT 2 and SOCFIT 3 at DAC. TFIT2 is
the new soft error rate (SER) response model developed in conjunction
with TSMC targeting 28HP process node. SOCFIT 3 focuses, at circuit
level, on assessing the overall failure-in-time (FIT) rate of large
integrated circuits (ICs) early in the design phase and produces a list
of major contributing elements on the impact of soft errors on
performance, especially at 65nm and below.
frequencies increase, margins decrease and packaging technologies grow
more complex with the advent of 3DIC and through silicon via (TSV), it
is increasingly necessary to analyze electromagnetic (EM) fields to
accurately model Chip-Package-Board systems. To date, commercial
solutions have failed to address the demanding needs of high capacity
and high speed while preserving accuracy in the electromagnetic
integrity (EMI) sign-off of large-scale systems. Nimbic's nWave full
wave 3D broadband field solver enables fast, scalable, accurate signal
integrity, power integrity and EMI analysis for very large designs.
Utilizing Nimbic's nCloud secure cloud compute platform further
accelerates and scales the analysis to allow designers to make the right
design decisions in near real time, achieving true EMI in a
cost-effective manner and enabling efficient EMI sign-off.
will be demonstrating how nWave and nCloud enables 3DIC/TSV and EMI
signoff as well as parallelism and cloud-computing for electronic
Booth # 2526
Oasys Design Systems
Designer™ is the first design tool for physical RTL synthesis of
100-million gate designs and produces better results in a fraction of
the time needed by traditional logic synthesis products. It features a
unique RTL placement approach that eliminates unending design closure
iterations between synthesis and layout. Based on Chip Synthesis™
technology, a fundamental shift in how synthesis is applied to IC design
and implementation, RealTime Designer deftly handles chip-level issues
that traditional block-level synthesis tools do a poor job of handling.
Oasys will offer continuous demonstrations of RealTime Designer on the
provides designers with guided flows to automatically implement
precise, hand-crafted quality design layouts. The Pulsic products -
Unity Analog Router, Unity Custom Digital Router, and Unity Custom
Digital Placer – provide automation where needed to deliver results
comparable to those created by hand. These tools tackle the
labor-intensive analog and custom design processes by providing a
guided, automated flow to introduce efficiency, flexibility and speed.
Pulsic will also be demonstrating the Pulsic Planning Solution, which
automates planning and top-level routing functionality. The Pulsic
Planning Solution — comprised of components for chip planning, power
planning, bus and repeater cell planning, and signal planning — is based
on Pulsic’s Unity technology.
Booth # 1908
migrates and DRC-corrects cell layout and makes sure the layout adheres
to all advanced design rules at 28nm and 20nm. It can be used to
migrate cells from 28nm to 20nm. Between similar technologies
(20->20, 28->28), update and modify design rules or cell
architectures, or 28->create derivative libraries. The tool generates
They will demonstrate the tool's ability to handle 20nm design rules in standard cell design.
Booth # 1402
Designer Memory+ is targeted to memory designers. They will demonstrate
how Memory+ runs the billions of Monte Carlo samples needed for high
sigma (up to 6-sigma) verification of bitcells and sense amps, giving
them visibility into the increasing effects of variation on design in
nanometer technologies. Memory+ will be demonstrated both from the
command line and from a graphical environment.
Variation Designer Low
Power+. To minimize power in today’s portable devices, designers must
consider numerous power states in their SoCs, and verify against
thousands of corner cases. They will demonstrate how its Low Power+ uses
Fast PVT meta-simulation technology, delivering a typical 2x-10x
productivity gain in design verification coverage across power states,
PVT corners, and layout RC corners. Attendees will see how Low Power+
actively finds and simulates only the worst-case corners while providing
predictive results for non-worst-case conditions.
Standard Cell+ is targeted to designers who deliver standard cell
libraries. They will demonstrate how Standard Cell+ can optimize a
library of cells across the increasingly significant variation effects
in nanometer technologies, to allow efficient migration of a standard
cell library to a smaller process node or second source. Attendees will
see how to leverage Solido’s meta-simulation technology to enhance
standard SPICE simulation and manage performance-yield tradeoffs.
Designer Analog+. Solido will demonstrate how its Analog+ product
builds on the well-established Cadence® Virtuoso® Custom Design Platform
to delivers simulation efficiency and design closure against worst-case
PVT corners and extracted n-sigma statistical corners. Analog+ delivers
a 10x average efficiency increase for PVT signoff, more consistent
Monte Carlo analysis with multiple stop-on-yield criteria, fast
extraction of statistical corners at a target sigma, and efficient,
intuitive, interactive design sizing.
Laker3™ platform was announced in April 2012. It enables the design of
analog, mixed-signal, and custom digital chips. The platform brings
gains in product performance and a brand new user interface with a
complete front-to-back OpenAccess design flow, robust process design kit
(PDK) offering, and extensive ecosystem of third-party tool
Laker Analog Prototyping automates the process of
analyzing advanced process effects and generating constraints to guide
circuit layout. Its enables automated constraint generation, layout
exploration, and rapid implementation in a single flow. Key features
include ‘smart’ placement techniques to automatically generate multiple
DRC-correct and routable options, hierarchical structure to handle
thousands of transistors, and full support for the complete range of
industry standard parameterized device formats, including MCells,
PyCells, C++ PCells, and Tcl PCells.
Laker Advanced Design Platform
(ADP) provides an entry point to drive the company’s Laker Custom
Layout Automation System by linking design intent and critical
constraints in schematic-driven layout (SDL) flow.
Layout Automation System for physical implementation with Magic Cell
parameterized device technology, rule-driven layout automation with
built-in DRC engine, and support for signoff-driven layout flow with
Mentor Calibre RealTime DRC platform.
Laker Custom Row Placer and
Laker Custom Digital Router enables designers to work within a single
custom IC layout environment to place-and-route both digital custom
cells and standard cells for either mixed-signal or custom digital
Laker Blitz Chip-level Layout Editor , also new at DAC2012,
is used for chip finishing operations to accelerate the handoff of
large, high density designs to manufacturing. It enables users to
easily load and view massive GDSII files, manipulate layout data for IP
merging and SoC assembly applications, and run cell, window or full-chip
DRC reviews and make layout corrections in single environment.
Tapeout of Gigascale Design - Learn how the latest capabilities
introduced in the Synopsys Galaxy™ Implementation Platform help both
digital and analog design teams capture, implement, verify and close
designs with optimal results. RTL synthesis, early design exploration,
custom design, digital implementation, extraction, timing signoff,
physical verification and the newly unveiled 3D-IC solution will be
covered in this presentation.
Advances in Achieving Gigahertz+
Performance - There is constant consumer demand for more functionality
with high, multi-Gigahertz performance for today's products. Learn how
the Galaxy Implementation Platform can help you deliver your high
performance designs with predictable results. The demonstration will
showcase advanced innovations in synthesis, place and route and signoff
Solution for DPT-Compliant 20nm Design - Find out what it
takes to implement DPT-Compliant 20nm designs with In-Design correction
and closure technology.
Achieving Fast Turnaround Time for
Analog/Mixed-signal Designs and Verification - Learn about Synopsys'
industry-leading solutions for analog/mixed-signal design, memory, SoC
verification and cell/SRAM characterization. Find out how you can take
advantage of the latest performance and comprehensive analysis features
in Galaxy Custom Designer®, HSPICE®, CustomSim™, FineSim® and
Silicon: Tanner’s analog design suite covers Schematic capture, SPICE
simulation, Layout, and Physical Verification. Now including Open
Access! Featuring enhanced design collaboration and layout
interoperability with Cadence Virtuoso 6 and other Open Access EDA
HiPer DevGen: A “silicon aware” analog layout acceleration
tool that recognizes and generates common structures; an essential tool
for high productivity and layout quality. HiPer DevGen automatically
recognizes and generates common structures including: Differential
pairs, Current mirrors, Resistor dividers, and MOSFET arrays.
Silicon A/MS: A cohesive Analog/Mixed-Signal flow that bridges Analog
and Digital Verification and adds Synthesis, Static Timing and Place
& Route. See their full-flow mixed signal offering integrating HiPer
Silicon with high performance tools from Aldec and Incentia.
Design Kits (PDKs) are a critical enabler for design enablement and
productive workflow. Learn about Tanner’s latest PDK and design flow
initiatives; including foundry-certified kits from Dongbu HiTek,
TowerJazz, and X-Fab.
Booth # 1126
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