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UVM—the star of DVCon 2011
Karen Bartleson
3/15/2011 11:11 AM EDT
What's all the buzz on UVM?
The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology (UVM), which is the latest standard ratified by Accellera. Instead of telling you about UVM myself, I decided to get information straight from one of the participants in the UVM effort, my colleague Yatin Trivedi.
Yatin told me, "The design verification community is rejoicing over the release of UVM 1.0. At DVCon 2011, the exuberance was quite visible. Let me just cite a few data points for any skeptic who might rush to call it 'irrational exuberance' of Alan Greenspan fame:
"Yes, UVM was the biggest story at DVCon 2011. So, naturally, the question arises—what is UVM?
"UVM stands for Universal Verification Methodology. It is a verification methodology, based on a class library defined using syntax and semantics of IEEE Standard 1800, also known as the SystemVerilog hardware description language. Thus it is a SystemVerilog-based verification methodology, not a new language. The standard is defined by the UVM 1.0 Class Reference document approved by the Accellera Board of Directors.
"UVM is a fine example of 'a standard developed by committee.' Accellera's VIP-TSC not only worked on the standard—the Class Reference Guide document—but it went one step beyond to provide a Reference Implementation for the documented classes."
I asked Yatin if the UVM effort followed any of The Ten Commandments for Effective Standards. He told me, "This industry-wide effort under Accellera demonstrates several commandments from the Ten Commandments of the Effective Standards:
Accellera's VIP-TSC working group will continue to seek ways to improve the UVM standard and enhance the reference implementation. If you wish to contribute, please join the VIP-TSC.
Karen Bartleson is senior director of community marketing at Synopsys, Inc. and author of The Ten Commandments for Effective Standards. Her blog for Synopsys is called The Standards Game.
The quite successful 2011 Design and Verification Conference was held last week. The most prominent topic at the conference was the Universal Verification Methodology (UVM), which is the latest standard ratified by Accellera. Instead of telling you about UVM myself, I decided to get information straight from one of the participants in the UVM effort, my colleague Yatin Trivedi.
Yatin told me, "The design verification community is rejoicing over the release of UVM 1.0. At DVCon 2011, the exuberance was quite visible. Let me just cite a few data points for any skeptic who might rush to call it 'irrational exuberance' of Alan Greenspan fame:
- a record number of attendees (more than 200) packed the all-day UVM tutorial
- standing room audience at Town Hall lunch meeting to talk about UVM and SystemC interactions
- full-house UVM panel that had six of the leading contributors answer Cliff Cummings' tough questions
- 12 of the 37 papers were about UVM
- best paper awarded to Adam Erickson on "evil" UVM macros! (photo)
- more than half the exhibitors showed their support for UVM
- 'Meet the Experts' in Accellera's booth was a great place for attendees to interact with, who else?, the UVM Experts (photo)
- numerous tweets with the hashtag #uvm, and a number of blog posts about UVM
- … and who can forget the rousing applause as each contributor was recognized for their dedication?
"Yes, UVM was the biggest story at DVCon 2011. So, naturally, the question arises—what is UVM?
"UVM stands for Universal Verification Methodology. It is a verification methodology, based on a class library defined using syntax and semantics of IEEE Standard 1800, also known as the SystemVerilog hardware description language. Thus it is a SystemVerilog-based verification methodology, not a new language. The standard is defined by the UVM 1.0 Class Reference document approved by the Accellera Board of Directors.
"UVM is a fine example of 'a standard developed by committee.' Accellera's VIP-TSC not only worked on the standard—the Class Reference Guide document—but it went one step beyond to provide a Reference Implementation for the documented classes."
I asked Yatin if the UVM effort followed any of The Ten Commandments for Effective Standards. He told me, "This industry-wide effort under Accellera demonstrates several commandments from the Ten Commandments of the Effective Standards:
- Collaborate on standards, compete on products: Not only major EDA vendors participated in this effort, but several users from competing companies collaborated too (notably, AMD, Cisco, Freescale, and Intel). Clearly, everyone was working towards the same goal.
- Start with contributions, not from scratch: UVM is built on top of the Base Class Library (BCL) of OVM, widely-used contributed technology such as VMM's Register Abstraction Layer (RAL) and phasing mechanism, support for Open SystemC Initiative's (OSCI) Transaction Level Modeling-2.0 (TLM-2.0), and the committee-developed Command Line Interface and Resource Manager.
- Be truly open: All Accellera standards are open to anyone who wants to develop and use them. They are also free. In case of UVM, the Reference Implementation is also open and available at no cost. Many leading EDA vendors have verified that the reference implementation is usable on their tools. The reference implementation is an Open Source project, so the support is provided by the community."
Accellera's VIP-TSC working group will continue to seek ways to improve the UVM standard and enhance the reference implementation. If you wish to contribute, please join the VIP-TSC.
Karen Bartleson is senior director of community marketing at Synopsys, Inc. and author of The Ten Commandments for Effective Standards. Her blog for Synopsys is called The Standards Game.
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