SoC proves a trial for test

The concept of system-level integration carries, implicitly and obviously, the idea that several different kinds of electronic structures can be integrated onto the same die. When we say system-on-chip (SoC), we think about processors, glue logic, memory and interfaces all residing on the same piece of silicon. But that thought, gratifying though it may be, is turning out to have some profound downstream implications-some of which may force designers to address a long-neglected problem with design methodology.

The problem is that an SoC comprising a mix of fast logic, noncritical logic, several kinds of memory structures and high-speed I/O creates two very serious demands. The first is for a mixed process that can actually implement all those things on one die. The second is for some methodology that can test the stuff.

For the process people, the problem is a hard one. The kinds of transistors needed for highest throughput are different from low-power transistors. The demands of high-speed, low-swing I/O require their own specialized pad-ring cells.

Foundries are addressing the process problem. The major players are adding modules to their umbrella CMOS logic processes to support faster or lower-power transistors, fast SRAM, precision high-speed analog and, in some cases, DRAM and even flash. Those additions aren't cheap, in terms of either mask layers or NRE. But they can be done.

The link in the chain that is having the most trouble adapting right now is the test floor. Fast logic testers, memory testers, communications analyzers and analog testers are all distinct pieces of equipment.

Designers say we are already seeing SoCs that require as many as five or six test insertions because of this problem. That not only drives test time-and expense-through the roof, but it severely limits the choice of test vendors and causes significant failure just from damage due to excessive handling.

Test system vendors are trying to respond with even bigger, higher-pin-count testers with more kinds of test capabilities. But that simply creates a bigger capital investment to be amortized over what promises to be a smaller number of chips.

The only practical solution will be greatly increased on-chip test capability. Built-in self-test must handle significant portions of the die and work with low-cost test systems to eliminate the need for high-speed or specialized external equipment. But that puts the responsibility for test right where it belongs, on the front-end design team.