VLSI papers weigh 65 nm, new circuits

AUSTIN, Texas — While technologists look to 65-nanometer nodes, circuit designers by and large are two generations back. So it's no surprise that as a string of 65-nm papers are delivered at the 2004 Symposium on VLSI Technology, fast circuits built at 130 nm will take center stage at the accompanying VLSI Circuits Symposium.

The meetings are planned for the week of June 15 in Honolulu, preceded by a satellite IEEE Workshop on Silicon Nanoelectronics on June 13-14.

The 65-nm process papers from NEC, STMicroelectronics, Texas Instruments, TSMC and others are clearly the highlight of the technology symposium. Researchers at NEC Corp.'s system devices research lab will discuss a 65-nm technology with a variable supply voltage and back-bias control to keep power consumption under control. Texas Instruments Inc. engineers will present a 65-nm technology with back-bias and voltage islands. A set of data-retention registers is used when the device is in sleep mode .

A team from the Crolles, France, development center of Motorola, Philips Semiconductors and STMicroelectronics will discuss its 65-nm CMOS platform, aimed largely at low-power applications. The abstract includes performance metrics for a test SRAM array with a cell size of 0.5 square micron, as well as for analog/mixed-signal transistors.

Taiwan Semiconductor Manufacturing Co. engineers will describe their 65-nm CMOS transistors, with the high-speed, general-purpose and low-power flavors using gate lengths of 40, 45 and 55 nm, respectively. The paper details the advantages of using a laser spike anneal process step instead of conventional rapid thermal annealing. The process results in improved drive current and less polysilicon depletion at the gate.

A separate TSMC paper discusses the reliability concerns of using relatively porous low-k dielectrics, with a k-value of 2.2, for interconnects targeted at 65-nm design rules.

TSMC also plans to describe a 45-nm SRAM cell created with a silicon-on-insulator (SOI) technology. A six-transistor SRAM cell takes up only 0.296 µm2 of area. The paper will discuss the advantages of SOI compared with bulk, including better control of the short-channel effects that plague such small devices. The transistors have gate lengths of 30 nm and operate as low as 0.6 volt, though nominal voltages are in the 0.85- to 1-V range.

Shinichi Takagi, one of Japan's leading researchers, will present work from Japan's government-supported MIRAI project that combines the advantages of silicon germanium — which creates higher mobility in the strained, active silicon layer — with the lower parasitics of SOI. The SiGe-on-insulator approach resulted in a 10x improvement in hole mobility in the PFET devices, the abstract reports.

IBM Corp. will present a 90-nm SOI process to build millimeter-wave devices. Two papers will discuss moving to different crystal orientations: 100- and 110-crystalline structures, for the NMOS and PMOS devices respectively.

Intel Corp. will present details of the 90-nm process technology it is now shipping, which includes local, or uniaxial, strained silicon. And Intel compares the advantages for mixed-signal and RF circuits of its NMOS technology with the silicon-germanium HBT approach to analog and mixed-signal circuits.

Micron Technology Inc. will present what appears to be the smallest DRAM cell size to date. By using a cell design that is six times "F" (F being the lithographically printable smallest feature), Micron engineers created a 0.036-µm2 cell size, using a technology with a 78-nm half-pitch created with a 193-nm scanner.

Samsung engineers will describe a NOR flash cell that measures 0.049 µm2. The approach requires pushing the ArF lithography tools to make contact holes that are 70 nm in diameter.

Samsung also goes to the Symposium on VLSI Technology with an SRAM cell of 0.16 µm2, using a stacked single-crystal technology and 80-nm design rules. The SRAM design stacks the load-PMOS and pass-NMOS transistors over the planar-NMOS pull-down transistors, cutting the cell size sharply.

More than a dozen papers describe emerging memories, including one from Samsung that applies the FinFET transistor design to DRAM arrays. STMicroelectronics and Ovonyx Inc. engineers will discuss chalcogenide phase-change memory research, with a trench cell structure that is compatible with a CMOS process. The cell size is 0.32 µm2 in 0.18-micron technology.

More information about the symposium is available at the conference Web site.