UMC opens R&D offensive on 45-nm front

Feeling the sting of claims that its 90-nanometer process comes up a little short, the R&D shop at United Microelectronics Corp. has been busy once again, demonstrating that it does like to tiptoe along the leading edge of technology.

In its counterattack, UMC has employed quantum physics, an atomic-level re-engineering of substrate crystalline structures and an old-fashioned PR blitz. The actions are intended to help mitigate any damage done by Chipworks Inc., a Canadian semiconductor engineering services company that recently said UMC did not use a low-k interlayer dielectric to make the Spartan-3 field-programmable gate array from Xilinx Inc.

The analysis firm also cast doubt on whether UMC's 90-nm chips were really that small, since the M1 pitch is 240 nm and the gate length is 70 nm. The International Technology Roadmap for Semiconductors says it should be 214 nm with 37-nm-long transistor gates. Other notable companies like Intel Corp. and Texas Instruments Inc. also fall short of these metrics, however.

The Chipworks claim kicked up a fuss, with UMC countering that Xilinx had opted not to use low-k intermetal dielectric materials, which are generally more unstable than fluoro-silicate glass. That set UMC on the offensive, trying to draw attention to its advanced research on process technology.

In June, at the VLSI Symposium in Hawaii, the foundry offered details about the substrate engineering techniques it is using to boost performance on 45-nm p-channel transistors by 30 percent or more. In recent IEEE publications, the foundry has also explored ways to enhance silicon-on-insulator (SOI) PMOS transistor performance, which also yields a 30 percent increase in drive current, according to the company.

UMC is studying a method by which it changes the orientation of the substrate crystal so that the holes hit fewer atoms as they move through the gate. It is only being applied to PMOS devices at the 45-nm gate length. The method increases hole mobility by 70 percent, UMC said, which trickles down to a 30 percent drive current increase.

Perhaps the most clever of the UMC projects in the lab, however, is one regarding partially depleted SOI. The foundry is using what is typically deemed a disadvantage-the quantum-mechanical tunneling effect-to increase drive current in PMOS transistors.

Usually, for the partially depleted SOI transistors, extra contacts are employed to control the floating-body effect created by excess electron charge buildup in the channel. In the UMC layout of a PMOS circuit, those contacts are unnecessary because UMC creates an overlap region where the gate can electrically control the body, helping to achieve a performance level that's even better than with the contacts alone.

"We are not the first ones to observe this behavior," said SC Chien, division director at UMC's central R&D department, "but we are the first ones to try to apply this kind of theory to help understand how to utilize this phenomena . . . in a circuit."

Both of the approaches are in line with UMC's strategy of putting more R&D effort into subtle changes that improve device manufacturability, rather than more aggressive techniques, such as triple-gate devices. With process complexity increasing exponentially, a little simplicity from time to time is refreshing.

Taiwan bureau chief Mike Clendenin can be reached at mclenden@cmp.com.