65-nm Intel CPUs due in late '05

AUSTIN, Texas — Moore's Law is alive and kicking at Intel Corp., which on Monday (Aug. 30) announced plans for volume production of its 65-nanometer processors. Now that Intel has successfully crossed over to 90-nm manufacturing, it expects to begin volume manufacturing of 65-nm processors in late 2005, with transistors that provide a 1.4x increase in raw frequency compared with the 90-nm technology.

At a time when some experts predict a slow death for the advantages of scaling, Intel is marching along to a two-year tempo. Just as the company's fabs, as of this quarter, now make more processors on its 90-nm process than on the 130-nm platform, Intel expects the crossover to 65 nm will come two years from now, in the third quarter of 2006. And scaling continues to double the number of available transistors per area, with an amazing 10 million of the 65-nm transistors in a single square millimeter of silicon.

With relatively few changes in the process recipe, analysts said the 65-nm node may prove to be a less difficult, and therefore less costly, transition than 90 nm, when Intel successfully introduced a low-k dielectric, nickel (rather than cobalt) silicide and a novel form of strained silicon.

The only big change in the 65-nm node is the introduction of sleep transistors between the SRAM blocks and ground in the cache array that will provide a "3x reduction in overall SRAM leakage," said Mark Bohr, director of process architecture and integration at Intel's Hillsboro, Ore., facility. Bohr emphasized that Intel's design teams may choose to adjust the Ion and Ioff characteristics, choosing to sacrifice performance for improved power consumption in mobile transistors.

At a briefing last week with reporters, Bohr said he remains unimpressed with the competition's shift to silicon-on-insulator, or SOI. Companies such as Advanced Micro Devices, Freescale Semiconductor and IBM claim that the reduced parasitic capacitances possible with SOI technology support significant performance gains, while reducing leakage at the substrate. "Junction leakage is just a tiny percentage of the overall leakage problem," Bohr said. "SOI does nothing at all in providing any benefits for source-drain or gate leakage."

Nevertheless, Bohr said, "everyone at Intel has gotten religion" when it comes to saving power. Technologists provide a process with a certain subthreshold slope, he said. It is up to circuit designers to choose whether to push performance for desktop and server applications, where the system thermal budget is about 90 to 100 watts, or to throttle back transistors to save on power for mobile systems.

Bohr said logic transistors generally can tolerate lower voltages than memory arrays, and hinted that Intel may move to dual-voltage designs in the future. The 65-nm logic transistors can operate at voltages as low as 0.7 V, and the prototype SRAM arrays also have been characterized at 0.7 V, he said. "We've done more in the power area than in the past."

The gate oxide thickness remains the same, at 1.2 nm, although some performance gain comes because the shorter 35-nm gate has about 20 percent less total capacitance on the gate. The 90-nm transistors had a 50-nm gate length.

The company has a "uniaxial" approach to strained silicon, which etches out a portion of the source and drain structures to add dabs of silicon germanium that strain the top, active layer of silicon. Intel has improved the approach somewhat, but the company is leery of revealing details. Strained silicon has proven to be a potent weapon for Intel, with 30 percent performance improvements compared with bulk transistors, Bohr said.

The carbon-doped oxide dielectrics in the interconnect stack will be extended. Bohr said some details about that will come in mid-December at the International Electron Devices Meeting in San Francisco. For the 65-nm technology, which Intel calls its "1264" process, Intel goes to eight layers of metal, one more than the 90-nm technology supported.

Also, while the number of alternating phase-shift masks may increase, Intel will be able to use a mix of 193-nm "dry" and 248-nm scanners — again, no big change from the 90-nm node.

The minimal number of process changes "bodes well for lowering the risk for Intel" as it moves the new process next year from Hillsboro to fabs in Arizona and Ireland, said Nathan Brookwood, an analyst with Insight 64.

Intel's technologists have argued that the 90-nm process had the least leaky transistors in the industry. Where Intel stumbled, Brookwood said, was in the design of the Prescott version of the P4 processor, where the transistor count zoomed up to 125 million transistors, compared with about 106 million for the comparable Athlon 64 processor from Advanced Micro Devices Inc.

Intel's previous P4, the Northwood design, drew only 82 W on a 130-nm process. With Prescott starting out at 90 W, and with minimal improvements in the benchmark ratings, Intel's customers balked. That led Intel to abandon the "megahertz is king" race, cancel its single-core Tejas design effort and move to dual-core designs at lower frequencies.

Brookwood said AMD's Opteron and Athlon64 designs may be able to move to dual-core implementations more easily that Intel can. AMD puts its on-board memory controller and the HyperTransport I/O block on one side of the die and connects them to the processor core on the other side with a crossbar switch. That switch-based design will make it fairly easy for AMD to move to a dual-core design.

"When AMD laid out the Opteron in 1998 and 1999, they had dual-core versions in mind," Brookwood said.

Technology shift

Intel, by contrast, has bigger changes ahead of it. The Prescott core is now married to certain features, such as data protection and 64-bit extensions. By 2006, Intel will need to move those features over to the more power-friendly Banias core, Brookwood said. "Intel will bring the features of its mobile technology to the desktop by 2006 with dual-core designs. It's all part of a serious technology shift away from megahertz," Brookwood said.

Mark Edelstone, who directs semiconductor industry research at Morgan Stanley, said during a recent presentation here that Intel has suffered from "serious misexecution" issues recently, ranging from Prescott's poor performance-vs.-power rating to key chip sets that have failed to meet their introduction targets.

Saying that AMD's Athlon 64 is "simply a better processor" than what Intel now offers for the desktop market, Edelstone nevertheless predicted that most corporate buyers will continue to take the safe road, i.e., buying servers and PCs based on Intel silicon. "Now is a good opportunity for AMD, but they are not going to take huge share from Intel," Edelstone predicted.

On the manufacturing side, AMD also is beginning to gain parity with Intel, said Brookwood. In terms of gaining "meaningful revenue" from its 90-nm process, Intel got on the board in the first quarter, while AMD ramped up its 90-nm process only recently. "That is roughly a 28-week gap, which by my reckoning is the briefest lag ever. AMD used to lag Intel by a year or even a year and a half," he said.

AMD has remained close-mouthed on 65-nm plans, bound to silence by its partners in the Fishkill, N.Y.-based process development alliance led by IBM Corp. and including Chartered Semiconductor, Infineon, Sony and Toshiba. AMD and IBM are expected to introduce some form of uniaxial strained silicon at the 65-nm node.