News & Analysis
Startup gauges impact of CMP on chip design
Richard Goering
9/17/2004 12:00 PM EDT
CMP is widely used for the planarization of multiple metal interconnect layers on ICs. Because CMP is pattern-dependent, floating dummy metal inserts are normally placed on a wafer. This extra metal increases capacitance, leading to delays on critical paths and to signal integrity problems that are rarely detected by current tools, Oh said.
UbiTech (San Jose, Calif.) is currently preparing an "intelligent" dummy-metal filler called ChampilDF that will support the use of foundry models. The filler avoids placing metal around critical nets. Currently under evaluation at a number of chip companies, including Qualcomm, ChampilDF is expected to be production-ready by the end of the year, and will initially target analog/mixed-signal designs, UbiTech said.
Oh worked on technology-CAD products at Hewlett-Packard Co. for 12 years, and was a developer of Rafael, a 3-D field solver initially sold by Technology Modeling Associates and subsequently by Avanti Corp. and Synopsys Inc.
He first tackled the CMP problem in 1996 in collaboration with MIT professor Duane Boning. Oh then went on to found Verilux Design Technology Inc., a provider of interconnect-modeling software. He sold that company to Aspect Technology, a provider of cell libraries, and stayed with Aspect until March 2001.
But Oh said he wanted "to use my background in interconnect modeling to solve the CMP problem. There is a conflict. If you want better planarity, you have to put in dummy fill, but that causes electrical problems."
Oh launched UbiTech in September 2001, and has been focusing on product development since then. He also had an important personal connection that helped him get started — with Silicon Valley entrepreneur Chong-Moon Lee, who is now chairman of UbiTech's board of directors.
Lee founded graphic-card manufacturer Diamond Multimedia Systems, where he is chairman emeritus. He is currently chief executive officer of the AmBex Venture Group, a venture capital firm, and has a portfolio of some 26 companies. Lee is also a consulting professor at Stanford University and a philanthropist who has endowed a center for Asian art and culture at the Asian Art Museum in San Francisco.
Lee acknowledged that he doesn't have an in-depth knowledge of EDA or chip design, but said he does have a lot of confidence in Oh, who was a high school friend of his niece and nephew. "I've known him for a long time and I know he is capable." Lee said he is looking for a CEO to run UbiTech so that Oh can return to engineering.
Lee said he is also looking for more venture funding for UbiTech, which has raised around $2.5 million thus far.
ChampilDF may fill a niche, but it's a critical one, Oh insisted. It has not been a hard sell to design teams, he said, especially since current RC extraction tools don't cover floating metal.
"It's not so difficult. Intuitively they know they have a problem, and the power users already have a problem," Oh said. "If we can make this a signoff tool, it could be a $200 million market."
Dummy-metal fill can have severe consequences on chip performance, Oh said. In a worst-case situation, he said, the dummy metal can increase capacitance by 20 to 25 percent on critical nets. This causes delays, as well as capacitive cross-coupling.
Chip designers today follow foundry design rules for dummy-metal fill, but doing that doesn't minimize timing and signal integrity problems, Oh said. It also requires a tedious manual process, makes it difficult to meet minimum and maximum density rules, disturbs device matching and may still result in a large variation in thickness. The problems grow worse as feature sizes drop below 130 nanometers.
UbiTech's Web site lists several upcoming products, some of which are aimed at process engineers. But the seven-person company is initially focusing its efforts on ChampilDF. It lets users block "problem" nets, insert dummy metal without disturbing the device matching in analog blocks, use various types of dummy shapes, use incremental runs to meet density rules and run Monte Carlo optimization.
Right now, said Oh, ChampilDF is "semiautomatic" in that a user specifies the critical nets for the dummy fill. That's good enough for analog designs, Oh said, because a designer will know which nets are critical. For digital designs, UbiTech is working on a version that will identify critical nets and block them automatically.
UbiTech is also working on getting copper CMP models from foundries. These are more accurate than the public-domain CMP models that are currently available from sources such as MIT, and offer better planarity control than dummy rules.
Meanwhile, UbiTech has joined third-party partnership programs from Mentor and Synopsys, and ChampilDF now interfaces to Synopsys' Milkyway database; an interface to the OpenAccess database will follow. UbiTech said it also plans to support Magma Design Automation's database.
UbiTech is not the only company offering a solution for CMP dummy-metal fill. But Oh believes it is ahead of competitors because of its strength in three key areas: interconnect modeling, CMP modeling and layout manipulation. Now the challenge is one of building a profitable business around a niche product.
