iRoC offers free Web-based tool to assess soft errors

SAN JOSE, Calif. — Soft-error analysis tool vendor iRoC Technologies Corp. (Santa Clara, Calif.) will this week introduce a Web-based tool that assesses the soft-error risk (SER) of chip designs.

According to iROC, the Soft-Error Analysis Web Tool enables design and quality engineers and managers to assess the risks of soft errors, which are transient faults caused by external radiation that affect the logic states of ICs.

The tool analyzes user input on chip size, process node, targeted process, amounts of memory and logic, type of memory and target application or market. It then processes the soft-error rate estimation, maps it against a RISK scale, and gives the user information on the SER failure-in-time (FIT) risk for that design in various market scenarios, the company said.

The tool also gives recommendations on steps that can be taken to quantify and also reduce the soft error FIT rate if the target application or industry requires it, iRoC said.

The tool is based on statistical data of soft error sensitivity that iRoC has accumulated from multiple efforts using its test vehicles, 3D simulations and soft-error protection services.

The free tool will be available Oct. 6 at iRoC's Web site.