Parser looks to spur SystemVerilog tool growth

The company this week is rolling out what it calls the first commercially available SystemVerilog parser, which it offers as source code to EDA vendors, not chip designers. The vendors are expected to build SystemVerilog products for synthesis, formal verification, emulation, acceleration and other HDL-based applications, speeding SystemVerilog's adoption.

Written in platform-independent C++, Verific's SystemVerilog parser supports the entire SystemVerilog 3.1 language definition, except for assertions, for which it supports 3.1a. Early adopters are using it in formal verification and HDL visualization tools, the company said.

This will lead to a proliferation of SystemVerilog tools, which will benefit designers, said Rob Dekker, the president of Verific (Alameda, Calif.). "For smaller companies, it takes away a significant amount of development they'd have to do," he said. "You will see the introduction of many more SystemVerilog tools in 2005 as a result."

Michiel Ligthart, vice president of operations at Verific, pointed out another advantage: If enough EDA vendors use the Verific SystemVerilog parser, then a SystemVerilog description that works with one tool will work with many others. A standard alone doesn't guarantee that, because different tools often support different language constructs, as is the case with Verilog 2001.

Verific has been selling VHDL and Verilog language parsers since 1998. Customers include Altera, Altium, @HDL, Dafca, Philips, Prover, Real Intent, Safe-logic, Sequence, Stelar Tools, Tharas Systems and Theseus Logic. The whole idea, said Dekker, is to save small EDA vendors, and internal EDA groups at semiconductor companies, the man-years of effort it would take to write HDL front ends on their own.

Dekker said he founded Verific after writing a VHDL front end for Exemplar Logic and concluding that it didn't make sense to go through all that work just for one company. All other providers of HDL-based tools have to go through the same process, reinventing the wheel.

"It makes a lot more sense for an external company to provide HDL front ends as software components," he said.

That is particularly true, he said, as language standards become harder to implement. "SystemVerilog is so complex that nobody in their right mind would think about writing the whole thing themselves just for an EDA tool," Dekker said.

He acknowledged, however, that big EDA vendors are more likely to write their own language parsers. But the SystemVerilog parser has been verified with simulators provided through partnerships with Synopsys Inc. and Mentor Graphics Corp.

Like other Verific tools, the new SystemVerilog parser includes an analyzer and elaborator. It parses and analyzes the entire SystemVerilog 3.1 language definition, using 3.1a for assertions. A complete parse tree is then available.

Static elaboration and RTL elaboration are fully supported for Verilog 2001, along with many but not all SystemVerilog constructs. Verific plans to expand the elaboration in additional releases during the rest of the year.

Verific also offers a SystemVerilog test suite, in addition to Verilog 2001 and Verilog-AMS test suites. Other parsers sold by the company support VHDL-1993, Verilog 1995 and 2001, Verilog-AMS and the Property Specification Language. Readers for EDIF, SDF and the Liberty library format are also available.

The SystemVerilog Parser is available now on Solaris, HP-UX, Linux and Windows platforms, starting at $100,000 for a royalty-free source-code license of the parser and analyzer. Time-based licenses start at $4,000 per month.