The first block complies with Serial ATA 1.0a on one side and has an Open Core Protocol wrapper on the other, allowing use with a number of 16-, 32- and 64-bit bus interconnect schemes that accept the OCP wrapper. When synthesized, the core requires about 60k gates, exclusive of memory. It is designed to work with commercial scan insertion and test pattern generation tools, and can achieve 97 percent coverage with those tools, QualCore said.

The dual serdes block supports SXGA+ and UXGA flat-panel display interfaces. Operating at up to 170 MHz, the core interfaces to 48-bit parallel data at CMOS logic levels on one side, and creates low-voltage differential-signaling links on the other. Maximum effective data throughput is 595 Mbits/second per LVDS channel when using dual-link mode at 85 MHz. The design includes a deserializer and a clock synthesizer per link.

This block is supplied as a pair of hard macros for 180-nanometer CMOS processes. Internal scan of the digital logic within the block is provided, as is overall boundary scan.