Programmable fuse IP finds life after RFID role

San Mateo, Calif. - One of the survival skills for a small company is agility. Conventionally, that means changing your product to suit the rapidly shifting needs of your customers. But it can also mean recognizing that technology you developed in pursuit of one market may have application in an entirely unrelated sector.

The latter is a venture investor's dream, since it multiplies revenue opportunities, intellectual-property breadth and exit strategies. But it can also be a marketing nightmare, creating disparate offerings that have unrelated sales cycles and serve unrelated customers.

Guess which side usually prevails.

This helps explain why a company primarily known for its aggressive stance in passive RFID tags might suddenly weigh in on electrically programmed fuse IP. The company is Impinj Inc. (Seattle), and the story goes like this.

RFID tags need local memory to hold data: identity, security codes, tamper-proof records and so forth. The ideal would be electrically programmable, nonvolatile memory that could be altered occasionally with an external device. But the expense of E2PROM or even flash processes cannot be justified in a market with potentially huge volumes and microscopic cost requirements.

That led Impinj to develop a novel floating-gate PFET structure that could be fabricated in a vanilla CMOS process-with no special structures or voltages beyond the 3.3-volt I/O supply-but that could act as a storage element. The device, announced in early 2003, could be used beyond RFID tags in any application that wanted a small amount (up to about 16 kbits) of nonvolatile memory and was willing to pay a significant area penalty for it.

Marketing the design as IP required creating a new division: the IP Products Group, under vice president Larry Morrell. Now, the company has decided to push the technology into yet another direction-the need for small banks of reprogrammable fuses in chip designs.

The fuses are perhaps mislabeled. The IP is actually a small bank of dynamic latches, automatically loaded at power-up from a shadow bank of nonvolatile floating-gate differential latches. So you get a logic 1 or logic 0 from the latch, not a shorted or open connection. You have to provide your own pass gate for that.

The evolution from nonvolatile RAM to fuse block was described as relatively simple. "The cell is similar to the cell in the Aeon memory array," Morrell said. "But because fuses must be bit-addressable, we moved overhead such as the addressing logic from the periphery of the array into the cell. The floating-gate PFET element is the same, so it is proven technology."

There is also a lock bit for each bank of eight fuses, permitting the user to render the devices one-time-programmable if desired. This bit is also implemented with a floating-gate PFET, Morrell said, but with a trick. "Ordinary PFETs come from the fab in random states before programming," he noted. "That would of course be a problem for the lock bits. So by altering the FET slightly, we biased them toward the unlocked state. That allows us to apply a strong programming pulse during test and force all the lock bits to the unlocked state."

The IP is supplied as hard-macro 8-bit blocks for implementations of up to 512 bits. Impinj quotes retention at 10 years and guarantees 1,000 write cycles. The chip area is about the same as for an equivalent number of metal or poly laser fuses, Morrell said. The company has verified the design in 0.25- and 0.18-micron TSMC CMOS.