Austin, Texas - Armed with test technology licensed from Freescale Semiconductor Inc., test consultancy SiliconAid Solutions has entered the electronic design automation tool market with a JTAG verification tool that is centered on boundary-scan description language (BSDL) inputs.

The company, based here, has been doing design-for-test consulting since 2001. Three of its eight employees have been working on software creation, led by SiliconAid chief scientist Bill Bruce, a former Motorola semiconductor test engineer who was the principal developer of an internal suite of Motorola JTAG tools.

Jim Johnson, a former Motorola test engineer and the CEO of SiliconAid, said the verification tool accepts BSDL files and meets the specifications of the IEEE's Joint Test Action Group 1149.1 standard. The tool can be added to any design flow to verify the JTAG logic and its associated BSDL. The tool reads a BSDL file and, using an interactive BSDL-intelligent editor, assists in modifying it.

The company's verification tool can output results either to a simulation environment or to a test-ready pattern set for use by the test engineer. After the verification process is complete, the tool creates test vectors used by the ATE hardware.

"Other vendors have tools that, when they produce a JTAG design, provide a testbench to verify that the design output of their tool matches what they think it should be. It is a go or no-go test. Our test is user-controllable and applicable to any JTAG design," Johnson said. Engineers can define tests and debug with them, or they can go beyond that to select individual options that customize the test patterns for debug, pattern enhancements, speed or fab process tests.

The tool is called the SiliconAid JTAG Environment JTAG Verification tool, or SAJE JTV. A one-year license is priced at $30,000, and a perpetual license also is available. The company plans to introduce SAJE JTS, a JTAG synthesis tool now in beta test stage. A debug tool, SAJE JTD, will be ready late this year, SiliconAid said.

Johnson said all of the tools are designed to work with just two sources of data: a Verilog netlist and the BSDL file. The BSDL file includes information that system engineers need to put a chip on a board for a board-level test strategy, while JTAG structures are used to isolate the chip and test it at the board level in situ, said Ed Scott, vice president of sales and marketing at SiliconAid.

"The BSDL file is what the chip guys pass on to the board engineers. Where we are unique is that we use BSDL as one of the primary inputs. It becomes a specification document for the JTAG design flow, similar to the way it serves as a spec for the system designers for how they use the JTAG file," Scott said.

Johnson said while the major EDA companies target engineers using a pure ASIC flow, SiliconAid's tools are suited to engineers who create custom chips or those seeking to reuse legacy designs.

"With our tools, there is not a lot of guessing or the need to learn EDA interfaces," he said. "That dramatically simplifies the flow, automates it and reduces the possibility of human errors."