DESIGN TOOLS: Startup preps for ESL design

Santa Cruz, Calif. — Offering what may be a key enabling technology for electronic system-level (ESL) design, startup Calypto Design Systems Inc. this week will field what it says is the first sequential-logic equivalence checker for ICs.

The tool, SLEC, serves two purposes: to verify that an RTL block is functionally equivalent to a higher-level block written in VHDL, Verilog, SystemC or C/C++ and to verify that sequentially different versions of an RTL block are functionally equivalent.

"The purpose of SLEC is to enable the move to a higher level of abstraction than RTL," said Devadas Varma, Calypto founder and CEO, who earlier was CTO of Ambit Design Systems and a Cadence Design Systems Fellow. SLEC is the first true sequential equivalency checker, Varma said, because it can compare blocks in which timing behavior may be completely different — including blocks that are untimed.

"If you look at previous combinational equivalence checkers, they did extend some behavior to simple sequential operations, such as retiming or special cases of pipelining. But we have no restrictions like that," he said.

Whether behavioral synthesis is used, several kinds of sequential design changes may be made during the design process. They include resource sharing, adding stages to pipelines and adding clocks in order to optimize power.

Further, said Varma, RTL designers often make sequential changes such as pipelining when they're trying to minimize power consumption. And that's difficult to verify with existing tools, he said.

SLEC works with SystemC, Verilog and VHDL. It can work with blocks at all levels of abstraction, including untimed C++. The input consists of the design source files and a TCL script that gives some setup information, such as initial starting states, clocking and reset sequences.

The information in that setup script, said Varma, is similar to what a designer might give synthesis tools. "It's quite different from what a verification engineer might need," he said.

From then on, the tool is automated. It's said to offer an exhaustive proof, and if there are differences in functionality, it provides a counter-example in the form of a simulation testbench or VCD format debugging file.

SLEC is a block-level tool. Mitch Dale, director of product marketing at Calypto, said the sweet spot for the tool is between 50,000 and 200,000 gates. Differences are typically found within minutes; fuller proofs generally take five to eight hours.

If a design exceeds several hundred thousand gates or sequential differences are large, SLEC can "run out of steam," Varma acknowledged. In this case it will give a partial, or bounded, proof.

SLEC is immediately available with Verilog, VHDL, SystemC and C/C++ support starting at $175,000 per year. SystemVerilog support is planned for the first half of 2006, Dale said.