A call to action for the EDA industry

Few EDA tool users are as demanding as Gadi Singer. For this 22-year Intel Corp. veteran, it isn't enough just to support the design of bigger chips. Singer helps Intel's diverse product groups develop "platforms" that include multiple chips and software, architectures that contain multiple CPUs and operating modes, and devices that represent the convergence of computing and communications capabilities. In a recent interview, Singer sat down with EDA editor Richard Goering and described what design automation vendors must do to support these advanced technologies.

EE Times: What concerns you in your current position at Intel?

Gadi Singer: My role is primarily around technologies and capabilities. We are helping the projects have a flow that supports the increased complexity of system design. We are working with both the projects and the EDA industry to enable and accelerate that.

Convergence is happening and is a major force that drives what we design as well as how we design. Convergence is having systems with strong computing and communications capabilities that are tightly integrated together. Within wireless design, the challenges include better coverage and broader communications. We're seeing a broad set of consumer devices that are smart, chic and untethered. Another major trend is the digital content, which today is used in multiple forms, such as music and video. And the final trend is having rapid development cycles.

All this is creating an environment for the types of [EDA] capabilities that are required. We need to drive two types of integration. Part of it is vertical integration, which is having a continuous development path all the way from the system level down to the transistor level. Today, not all the pieces are there and it is definitely not integrated.

We also need what I would call horizontal integration. With that, you have multiple types of components or multiple parts of designs within components, and the ability to support the platform development across multiple domains and across ICs.

EET: What are the challenges associated with platform-oriented design?

Singer: A platform is a combination of multiple ICs and the software that together creates a complete device and a complete solution. For example, a notebook has multiple components and has layers of software. [Likewise] a handheld device.

There is a growing need to understand this overall platform together, rather than just looking at the pieces and doing a very loose assembly of them. Power, which is a major element, needs to be optimized and understood at the platform level. If you look at battery life, it needs to be understood as a combination of all the ICs and usage modes and how the software interacts with those ICs.

EET: What's needed for design at the platform level?

Singer: We need to have an abstraction level where we can look at the overall platform and do modeling at that level, where we can do validation at the level of the platform and we have a way to refine from that level and tie down to the RTL. We have a very good flow generally to go down from RTL to layout. However, RTL was established two decades ago. Since then, complexity has grown severalfold and the EDA industry has not provided a similar level of support for design and refinement at the next level. This is a level that is an absolute requirement to deal with the growing complexity.

Another element that is important is hardware-software co-design, because if you look at the functionality of those platforms, they're comprised of tight interactions between hardware and software.

EET: It sounds like you're talking about electronic system-level design. What kinds of ESL capabilities should the EDA industry provide?

Singer: One has to do with modeling — the ability to capture the design at the platform level, and do simulation and experimentation with this model. A second capability is validation, which should be done first against some predefined specs or expectations. And the third thing is having tools that are either synthesis tools or assisted tools to migrate from high-level modeling toward more-specific logic designs.

We need to understand how much should be automatic vs. assisted. We were spoiled by the great convenience of logic synthesis. When we try to define the next level up in the industry, we're looking for a similar level of capabilities. I think this expectation hinders us, because it might take some time before we come to the same level of automation.

EET: What about functional verification?

Singer: I think verification is one of the key focus areas for faster time-to-market. It is easier to design faster than it is to fully validate faster. We need to look at validation as a continuum all the way from the platform level to the top system-on-chip level and down to components.

Functional validation faces an increased challenge from what I call multivertex systems. That means the platform has multiple points of concurrent execution. If you look at platforms that are created with dual cores, and in the future with multiple cores, you're looking at multiple communications devices on the platform, each with their own software stack and with their own activity. We need to create validation that understands the interaction between those different vertices in different modes.

EET: Many platforms include analog and mixed-signal components. What's needed to model that?

Singer: Let's talk about wireless design. Usually wireless design has subsystems that include the MAC [media-access controller] and baseband. There is high-speed digital circuitry, analog and RF. There are good point capabilities for circuit analysis and RF, but there aren't suites of capabilities that allow a comprehensive development of the RF and the analog. What's especially missing is a way to support the whole flow, all the way from something that is software driven like the MAC to very high-speed RF.

We need to have the capabilities that help us understand the noise implications. An example is when you have high-speed digital circuitry close to some analog circuitry. The digital circuitry is creating noise and is creating temperature effects that are impacting the analog, but the tools we have for this space usually are not tuned for the finer physical impacts on sensitive circuitry. Today we have to stitch together solutions.

EET: How about optimization?

Singer: When we look at constraints such as performance, power, battery life and noise, it is becoming harder to separate those and optimize for each of them separately. We need to have capabilities to do the trade-offs, to understand how much performance we lose if we gain that much battery life. Today we do this concurrently, but we're using a lot of human glue.

EET: What issues are most important at 65 and 45 nanometers?

Singer: When you continue Moore's Law, you create new levels of difficulty. We've talked about having designs with 1.7 billion transistors and tens of millions of logic gates. So we need to be able to deal with the overall complexity of the design and have a higher capacity with tools.

For DFM [design-for-manufacturing], we need to have a better understanding of manufacturing considerations when the design is being finalized at 65 and 45. The other aspect is power-related analysis. When you have hundreds of millions of transistors, power is becoming a further area of focus.

EET: What should EDA vendors do to improve power analysis?

Singer: We need to understand power at a higher abstraction level. A lot of the power decisions have to do with interaction between software and hardware. Some of the power tools that we have are tied to very specific implementations, or they have their own kind of power model. We also need to make sure we have power capabilities integrated into the same model that we use for basic design.

EET: How is the EDA industry doing on tool interoperability?

Singer: Today we have a rudimentary capability to do that through some standard file formats. This is not sufficient and this by itself could be a limiter to enabling semiconductor companies to move as quickly as they need to on platform-oriented design.