Whizzy new tools dangled at DAC

ANAHEIM, Calif. — While it's tough to discern any one theme arising from the 2005 Design Automation Conference, the show floor this week in Anaheim, Calif., will be bursting with a wealth of ideas that should help close the gap between what nanometer silicon processes can provide and what IC design tools allow.

Innovative technology on view at the 42nd DAC not only analyzes IC leakage and dynamic power but helps optimize for them as well. New tools may help make electronic system-level design more feasible, ease functional-verification woes, address the growing challenges of variability in IC design and make design-for-manufacturability practical for design teams.

As is often the case, much of the new technology comes from small vendors and startups. And much has yet to be proven in the field. Until technology is in the hands of users and has been pressed into service to design real chips, there's no way to know if it's truly the godsend the provider claims.

Since late April, however, a number of potential breakthroughs have emerged. Among these are Power Optimize Gold and Power Plan Gold, from power-reduction specialist Golden Gate Technology Inc. These tools can reduce IC power consumption by up to 25 percent, said Dennis Heller, Golden Gate's CEO.

Power Optimize Gold promises to reduce leakage and switching power while meeting constraints for timing, signal integrity and electromigration. It uses a patent-pending technology called WiresFirst to minimize the total capacitance on critical clock and signal nets through routing optimization and isolation techniques. Power Plan Gold creates designs with multiple voltage islands by automatically generating power grids.

Power reduction is also the goal for startup Azuro Inc., whose PowerCentric tool combines clock tree gating and clock tree buffering into one postplacement step that can potentially replace clock tree synthesis tools. Clock tree gating today is done as part of RTL synthesis, said Azuro CEO Paul Cunningham, while clock tree buffering can't be completed until after placement. PowerCentric, he said, is a "complete clean-sheet rewrite of clock tree gating and clock tree buffering" that can find a better clock-gating topology than traditional methods allow.

Also worth noting is Apache Design Solutions Inc.'s PsiWinder, a critical-path analysis tool combining dynamic-power integrity and crosstalk noise analysis. And Synopsys Inc.'s PrimeRail claims a "hybrid" capability for voltage drop and electromigration signoff by merging static and dynamic IC analysis.

Bringing power analysis to a higher level, ChipVision Design Systems Inc. will come to DAC with Orinoco 2005.1, said to be the first electronic system-level (ESL) design tool that can estimate leakage power as well as dynamic power.

ESL arsenal grows
One major ESL announcement at DAC comes not from a single vendor but from the OpenSystemC Initiative, which has rolled out the SystemC Transaction-Level Modeling (TLM) standard 1.0. With heavy backing from leading EDA vendors and user companies including Philips and STMicroelectronics, this standard may help foster a new generation of transaction-level design and verification tools.

The new TLM standard defines application programming interfaces and provides a library that implements a foundation layer. It's available under an open-source license at www.systemc.org. Summit Design Inc., meanwhile, will come to DAC with Vista 1.1, which offers a TLM viewer for SystemC simulators.

Startup Calypto Design Systems Inc. promises to make ESL design practical with the first sequential equivalence checker. Its SLEC tool can verify that an RTL block is functionally equivalent to a higher-level block written in VHDL, Verilog, C/C++ or SystemC, and can also verify that sequentially different versions of an RTL block are functionally equivalent. "The purpose of SLEC is to enable the move to a higher level of abstraction than RTL," said Devadas Varma, Calypto's founder and CEO.

SLEC also fits into the functional-verification space, an area that will draw its share of attention at DAC. One company claiming new technology is Tharas Systems Inc., which bills its Virtual Connect as the first RTL-accurate "virtual emulation" capability. The product creates software models of system-on-chip platforms, allowing concurrent hardware/

software development, the company said. Sanjay Sawant, director of marketing and business development, called virtual emulation the "next generation of emulation technology," intended to sidestep today's "hardware nightmare."

Two companies are touting new technology that helps users fully exploit all the features in the emerging SystemVerilog language. Mentor Graphics Corp.'s Questa products are based on a single-kernel verification engine that encompasses an HDL simulator, a constraint solver, an assertion engine and functional coverage. And Axiom Design Automation (formerly @HDL) is offering MPSim, a SystemVerilog simulator targeted at multiple-CPU workstations.

Cadence Design Systems Inc., meanwhile, is taking another run at assertion-based verification with Incisive Formal Verifyer, a tool that promises unprecedented ease of use. This is formal analysis "for the masses," said Michal Siwinski, product-marketing director for Cadence's Incisive group.

In RTL-to-GDSII implementation, Synopsys seems proudest of something it will not show at DAC — wire load models. Its latest Design Compiler release claims to eliminate wire load models with a new "topological" capability.

Although its 1Team Implement offering dates back to early April, Atrenta Inc. is a company to watch at DAC. It is rolling out a suite of tools based on its "predictive development" technology, including 1Team Implement, a silicon virtual-prototyping tool that can take a design from a partial RTL description to a placed netlist.

Physical-synthesis provider Sierra Design Automation Inc., meanwhile, is claiming a breakthrough in handling "design for variability." Its latest Pinnacle release promises to concurrently optimize timing, area, power and signal integrity across all operating modes and corners, as opposed to one corner at a time as traditional tools do.

"We've come up with a way that you can do it all in one shot," said Shankar Krishnamoorthy, Sierra's CTO. That means users can consider variations from different modes, such as sleep or standby; different process, temperature and voltage corners; and on-chip metal variations that affect interconnect resistance and capacitance.

Speaking of variations, newcomer Gradient Design Automation will show at DAC its Thermal FireBolt, said to be the first tool that can account for the electrical effects of chip packaging and ambient conditions on the internal temperature distribution of the chip. The tool provides a full 3-D temperature map. The company said ignorance of thermal effects can force designers to apply timing and power margins of 30 to 40 percent.

For its part, Magma Design Automation Inc. will be showing off its Cobra release, which the company said includes innovative technologies in such areas as statistical timing analysis and design-for-yield. But what may grab more attention is the company's recently announced Quartz-DRC. This competitor to Mentor's market-leading Calibre product promises to run design-rule checking on any IC design in two hours or less on a distributed network of Linux workstations. The technology behind Quartz-DRC is based on a new approach to fine-grained parallelism, said John Lee, Mojave's founder and now the general manager of Magma's physical-verification business unit.

Statistical yield modeling
Design-for-manufacturability (DFM) will also take the spotlight at DAC. Startup Ponte Solutions Inc. will preview statistical yield-modeling software for IC designers. Its encrypted models provide a way for foundries to release yield information without compromising proprietary data. Most DFM tools use foundry design rules, said president and CEO Alex Alexanian. But statistical yield modeling is far more accurate and less cumbersome, he said — if you can get the information from the foundry to do it.

For its part, lithography-simulation provider Sigma-C, which already sells software to process engineers, is aiming its new Solid+ product at design teams. The German company hopes Solid+ will become the lithography-simulation equivalent of Spice modeling.

One technology that is not an EDA tool by itself, but could potentially change EDA as we know it, is Silicon Navigator Corp.'s Rocket Framework. It provides such features as a graphical user interface, Tcl scripting, an incremental timer, and schematic and layout visualization on top of the OpenAccess database.

That means EDA startups, internal CAD groups and researchers can take their algorithms and develop "engines" without having to deploy an underlying data infrastructure. That takes away much of the work behind developing a production-worthy EDA product and opens the door to a more widespread proliferation of technology.

Finally, silicon intellectual property will also be featured at DAC. Denali Software Inc.'s Dataplex data subsystem provides configurable interfaces to off-chip DRAM, flash and serial ATA hard-disk-drive storage. It can thus bring data directly to DRAM without going onto the system-on-chip bus.

"We see this as a new category of intellectual property, an integrated data-management subsystem," said CEO Sanjay Srivastava.