News & Analysis

IBM's formal verification platform optimized for large chip designs

6/13/2005 9:01 AM EDT

ANAHEIM, Calif. — IBM Monday (June 13) released the newest version of IBM Design Verification (DV) RuleBase PE, the company's formal verification platform for ASIC design.

IBM said RuleBase now enables engineers to more rapidly verify larger and more complex chip designs while harnessing the power of parallel computing. The improved framework allows for easy integration of third-party formal verification engines, the company said.

The latest version of RuleBase includes new algorithms for the verification of assertions across very large designs.

"We can now verify large-scale designs at a fraction of the time required by other formal verification techniques," said Yaron Wolfsthal, manager of the IBM Formal Methods group at the IBM Haifa Labs. "We feel the platform's versatility and interoperability are very real benefits that will empower our customers and help promote the adoption of assertion-based design flows and formal verification, using the PSL industry-wide standard."

RuleBase will be offered through IBM Engineering and Technology Services. Pricing information was not disclosed.





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