News & Analysis
Applied preps MOCVD for high-k gates
Mark LaPedus
8/8/2005 8:06 PM EDT
Applied (Santa Clara, Calif.) is also expected to make its long-awaited entry into the ALD tool market for gate-stack applications.
The chip-equipment giant has developed an MOCVD module within its Centura 300-mm platform for use in high-k gate-stack applications, said Pravin Narwankar, high-k engineering manager for the Front End Products Division at Applied.
The MOCVD module “is shipping,” Narwankar said in an interview after a presentation, which was given at the AVS 5th International Conference on Atomic Layer Deposition 2005 here on Monday (August 8).
MOCVD technology is expected to give chip makers an early and cost-effective solution to deploy high-k gate-stack films, as compared to rival ALD-based tools in the marketplace, he said.
“CVD is a manufacturing-worthy process,” he said. “Cost-of-ownership is a problem with ALD. Throughput goes down by almost half with ALD.”
One vendor disagreed, saying that ALD will become the dominate tool technology for high-k dielectrics. “ALD will be adopted at 45-nm,” said Tae-Young Lee, vice president and chief operating officer for Vesta Technology Inc. (San Jose), the U.S. sales arm for South Korean ALD tool specialist IPS Ltd.
Choices galore
Indeed, chip makers are currently evaluating a number of tool and material technologies for high-k, gate-stack applications at the 45-nm node and beyond for good reason.
Device manufacturers are scrambling to reduce leakage in cutting-edge devices and traditional materials are running out of gas. “The 45-nm transistor is at the cross roads,” Applied’s Narwankar said. “Silicon dioxide has hit the wall at 65-nm. Silicon dioxide has also hit the wall for low-power applications.”
To enable high-k for gate stacks, chip makers are evaluating ALD, plasma enhanced ALD, MOCVD and related tool technologies. ALD deposits ultra-thin films one atomic layer at a time. Unlike conventional deposition technologies, ALD offers control of the thickness and uniformity of monolayer films of less than 100 angstroms. In comparison, MOCVD is a method for preparing epitaxial structures by depositing atoms on a wafer substrate.
On the materials side, meanwhile, chip makers are also looking to develop high-k gate stacks, based on hafnium-based films. Due to their intricate composition, advanced films targeted for 45-nm high-k gate dielectrics, such as hafnium oxide (HfO), hafnium silicate (HfSiO) and hafnium silicate oxynitride (HfSiO/N), as well as metals like ruthenium, pose challenges at the film-removal and other process stages.
To address these challenges, Applied plans to hedge its bets and field a range of tools for high-k gate-stack applications, including ALD and MOCVD. “We will have both technologies available,” he said. “It’s driven by economics.”
It is also scrambling to enter this field — and for good reason. Applied, TEL and others sell tools for traditional gate-stack applications, based on silicon dioxide or oxyntrides materials. In 2004, Applied led the industry in transistor gate fabrication technology with its Centura DPN Gate Stack system, achieving 71 percent market share, according to market researcher Gartner Dataquest.
Applied is also no stranger to ALD. It sells CVD and ALD tools for capacitor and barrier seed applications. Expanding its efforts in ALD and related markets, the company last year acquired Torrex Inc. With the acquisition of Torrex, Applied gained a new ALD product, based on a mini-batch technology.
With its single-wafer Centura tool, meanwhile, Applied at the ALD conference presented new data based on its MOCVD technology. Using MOCVD technology and HfSiO/N materials, Applied claimed to process a device with an EOT from 15.5 to 12.5 and film thicknesses of 42.39 angstroms with uniformities of 1.073 percent.
Using ALD technology with similar materials, the company claimed to have processed a device at 28.5 angstroms with uniformities of 0.59 percent.
