Industry delays high-k gates at 45-nm

SAN JOSE, Calif. — The semiconductor industry’s planned shift towards complex high-k dielectric insulator materials for gate-stack applications at the 45-nm node has been delayed, according to an executive from Applied Materials Inc.

For some time, chip makers have been scrambling to reduce leakage and power consumption in their cutting-edge devices. Traditional silicon dioxide material for gate-stack applications is one of the culprits for leakage and the technology is running out of gas.

Originally, chip makers hoped to replace silicon dioxide materials with new and complex high-k dielectric films at the 45-nm node. But there are whispers among chip makers that the technology will be pushed out, forcing vendors to deploy silicon dioxide and oxynitrides for the 45-nm node.

It is unlikely that the semiconductor industry will deploy “high-k at the 45-nm regime,” said Mark Pinto, chief technology officer and senior vice president of the New Business and New Products Group at Applied Materials (Santa Clara, Calif.), at a press event.

“There are tools out there [for high-k production]. We have tools out there,” Pinto said. “There is no one in production today [with chips based on high-k materials]. Most companies are using oxynitrides materials for the 45-nm node.”

One of the overall problems with high-k at the 45-nm node is the integration issues, namely the “Fermi-level pinning effect ”(see Sept. 2 story). And due to their intricate composition, advanced films targeted for 45-nm high-k gate dielectrics, such as hafnium oxide (HfO), hafnium silicate (HfSiO) and hafnium silicate oxynitride (HfSiO/N), as well as metals like ruthenium, pose challenges at the film-removal and other process stages.

High-k dielectric materials were supposed to ride to the rescue about now, improving the electric-field strength in the channel and thus reducing leakage for a given dielectric thickness. The plan was to combine high-k with a metal gate, which would give a superior work function and eliminate the depletion region that forms at the bottom of the polysilicon gate electrode.

Some chip makers may deploy a form of high-k in their processes. Some may use “poly on top of high-k for ultra low power technology,” Pinto said.

But chip makers have not publicly said they would delay their overall high-k plans, but there are signs the technology has been pushed out. “I can’t comment on Intel’s plans,” said Mark Bohr, director of processor architecture and integration at Intel Corp.'s Hillsboro, Ore., laboratory. “It is true that some of the companies are saying that [high-k is delayed at 45-nm].”

Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), for one, has dropped hints that high-k would not be ready for the 45-nm node (see August 15 story).

Texas Instruments Inc. claimed Monday (Sept. 19) it had solved the problem of excessive leakage current at the 65-nanometer manufacturing process node with the transfer of its SmartReflex power and performance management technologies from the 90-nm process node to the 65-nm node.

The SmartReflex technologies are a combination of adaptive devices, circuit design and software designed to solve power and performance management challenges at smaller process nodes, TI said. This is instead of or in addition to specifically attacking gate leakage current through the use of high-k gate insulator materials, a quest that has been pursued by the industry for many years (see Sept. 19 story).