News & Analysis
SystemVerilog verification manual published
9/21/2005 4:30 PM EDT
The VMM, which was announced in February 2004, seeks to be to SystemVerilog verification what the Reuse Methodology Manual (RMM) has become to intellectual property (IP) reuse. The RMM, first published in 1998, has become the seminal text that defines a comprehensive approach to intellectual IP reuse in chip designs — it is currently in its fifth edition and has been translated into several languages.
According the Springer (New York), the VMM documents years of know-how and industry best practices for architecting advanced, efficient verification environments using industry-standard SystemVerilog assertions, testbenches and functional coverage. It was written by Janick Bergeron and Eduard Cerny of Synopsys, and Alan Hunter and Andrew Nightingale of ARM and, according to the publisher, was peer reviewed by verification engineers from more than 30 semiconductor companies.
According to Steve Smith, Synopsys' senior director of RTL verification marketing, the VMM was created to bring what had been proprietary technology to users, adding verification features to what has been a very popular design language.
"The idea was to bring to the masses proven mechanisms for using SystemVerilog in verification, building on proven methodologies that have been out in the market for several years," Smith said.
The Verification Methodology Manual for SystemVerilog is available now from Springer for $129.00 U.S. The publisher said the book could be ordered from its Web site.
Synopsys (Mountain View, Calif.) made several announcements Wednesday to coincide with the book's publication.
The company announced the availability of the SystemVerilog source code for its implementation of the VMM Standard Library, a base-class library specified in the VMM that is said to more quickly and easily enable users to adopt the verification techniques and methodology advocated by the book. Supplying the source code, which is available at no charge to customers of Synopsys' VCS register transfer level (RTL) verification solution, could save design and verification engineers that do not have a background in advanced verification methodology several months, according to Phil Dworsky, Synopsys' director of strategic alliances.
Synopsys also said it has added to its DesignWare IP library synthesizable IP for the ARM AMBA 3 AXI on-chip bus protocol. According to Synopsys, the synthesizable IP, combined with the available DesignWare Verification IP for AMBA 3 AXI, enables designers to more easily integrate the protocol into their system-on-chip (SoC) designs while simultaneously reducing risk and speeding time-to-results. The synthesizable IP for the AMBA 3 AXI protocol is used in high-bandwidth, low-latency, high-performance designs, the company said.
The Synopsys DesignWare synthesizable IP for the AMBA 3 AXI protocol is available now to early adopters as part of the DesignWare Library, the company said, with general availability expected in the first quarter of 2006. DesignWare Library licensees have access to this IP at no additional cost. RTL source code is available for license separately, on a pay-per-use basis.
Dworsky characterized the availability of the source code and the synthesizable IP as providing users with the building blocks they need to use SystemVerilog for verification. These elements provide a repeatable mechanism by which users can standardize a methodology, he said, noting the importance of standardized methodology to allow design teams scattered throughout the globe to "work from the same playbook."
Finally, Synopsys said DesignWare Verification IP for the AMBA 3 AXI was the first to earn the AMBA 3 Assured" logo certification from ARM (Cambridge, England). The logo indicates that the verification IP has been shown to correctly implement the AMBA 3 AXI specification, as defined by the assertion-based AXI protocol rule sets available from ARM, Synopsys said.
