Software limits multi-core ICs, panelists say

SANTA CLARA, Calif. — Multi-core ICs promise efficiency and performance, but will require new programming models that hide software and hardware details, according to panelists at the GSPx 2005 conference here Tuesday (Oct. 25).

With multi-core ICs, said Daya Nadamuni, chief analyst at Gartner Dataquest, "software is both the problem and the opportunity." She noted that systems-on-chip (SoCs) have not only hardware, but also a hardware/software binding layer, real-time operating system (RTOS), middleware, and applications software. Miss any of these components and you have problems getting to market, she said.

Nadamuni said that SoCs comprised 16 percent of the ASIC market and 31 percent of the ASSP market in 2004, and are expected to show rapid growth. The largest consumer, she said, is the handheld market, with automotive electronics expected to be a growth area in the future. But success depends on managing a "software explosion," she said.

The price of failure can be high, Nadamuni said. In China in 2004, she said, 65 percent of sub-$100 DVD players were returned, many due to software failures.

Steve Krueger, core IP architect at Texas Instruments, discussed his company's OMAP 2420 multi-processor SoC, which includes an ARM 11 general-purpose processor, a programmable DSP, and a number of special-purpose processors for such tasks as video and graphics. He noted that special-purpose processors can be 10 to 20 times more efficient than general-purpose processors, and can provide the required performance for fewer MHz than general-purpose processors.

But there's a price. IP integration is a big issue, Krueger said. Another challenge is a conflict between asynchronous IP interfaces and strict real-time requirements, which tend to conflict with asynchronous behavior. Power management is also a challenge, and has led TI to segment chips into a large number of power domains with unequal supply voltages. A final challenge is memory performance and coherence.

"The principal problem of multi-core is how you map software applications into increasingly complex hardware," said Mark Lippett, CTO of Ignios Ltd. "The challenge is the programming model and the efficiency it delivers."

A good programming model, said Lippett, is all about transparency — that is, hiding hardware details from the programmer. He said programmers shouldn't have to worry about scalability, performance, access, location, failure, migration, or concurrency. And yet, he noted, "we cannot sacrifice real-time efficiency to achieve this level of abstraction."

What's needed, said Lippett, is a "platform abstraction layer" to map software applications to hardware. Ignios provides such a layer in its SystemWeaver product, he said.