Quality, easy integration are on IP 'must have' list

Increasing cost and complexity in semiconductor intellectual property has forced system-on-chip (SoC) manufacturers to examine the make-vs.-buy trade-off with renewed interest. However, while those trends have mitigated some of the risks associated with new IP development, new challenges have crept up. The challenge going forward is one of IP selection by teams with partial or nonexistent expertise in the IP cores being considered.

Some of the key areas where we see IP selection trends evolving over the next two to three years are in IP quality evaluation, ease of IP integration, performance validation, signaling of vendor maturity and the ability to easily reconfigure IP. Our predictions for the future in these areas are presented below.

IP quality
IP quality is being addressed by industry consortia such as the Virtual Socket Interface Alliance's QIP metric. Currently, attempts at defining IP quality are ad hoc or company-specific. The VSIA QIP attempts to bring measurability to assessing the quality of an IP core from a vendor by assigning a quality score that captures various metrics including vendor capability, design practices, and IP core documentation and deliverables. In the future, this metric could serve as a useful tool for designers to assess whether a particular IP core meets minimum quality standards and if the IP vendor is "worth" engaging with. While the QIP score cannot eliminate the need for due diligence, it provides a consistent baseline of IP quality that can be used to filter IP providers.

IP integration
IP integration has always been a key challenge in making IP truly reusable. IP cores are becoming more complex, and integrating them into a design can be an extremely difficult and time-consuming task. Each

IP core includes dozens or even hundreds of files that are used to handle different configurations, operating modes and applications. The designer procuring these IP cores — in the absence of any in-house expertise — has to rely on data books and manuals supplied by the IP vendor to understand the various core options and how the core should interface with all the other cores in the design. The designer would then have to hand-connect the various IP blocks along with the application-specific logic. The time required to do so is dependent on the complexity of the design and the customer's expertise, but a great deal of time is usually required before a design is ready for initial synthesis and verification. From the IP vendor's perspective, significant support resources are also tied up in assisting the customer with this process. All these steps add time, cost and opportunities for error.

IP cores are becoming more complex, and integrating them into a design can be an extremely difficult and time-consuming task.

A new trend that is emerging in the industry, spearheaded by the Spirit consortium, is the move toward XML-based schema to document information about the IP core and how it can be used in a standard way understandable by designers and their design environments. Standards-based, well-defined interfaces allow many tools the ability to access and understand the underlying IP and its relationship to other IP blocks. Platform Express, one such tool from Mentor Graphics, provides a graphical user interface that enables designers to drag and drop IP blocks, buses and other SoC components onto the design and connect them in a simplified way compared with hand connections previously required with RTL. Widespread adoption of XML-based IP descriptors will enable designers to reuse IP blocks without the time and effort required to integrate them into designs. IP vendors will also benefit from reduced support calls.