News & Analysis
Intel tips 45-nm process, demos chips
Mark LaPedus
1/25/2006 12:02 PM EST
Compared to its 65-nm process, Intel (Santa Clara, Calif.) claims that its new 45-nm technology has a two-fold improvement in transistor density, a 20-percent jump in switching speeds and a 30-percent reduction in power. Since late last year, Intel has been shipping microprocessors based on its 65-nm process.
Intel’s 45-nm process, dubbed P1266, is said to incorporate copper interconnects, low-k dielectrics, strained silicon and other features. The company did not disclose if it would deploy silicon dioxide or high-k dielectric films for the critical gate stack.
It plans to manufacture 45-nm devices by using 193-nm “dry” lithography scanners — instead of immersion tools, as previously expected by some analysts.
With the 45-nm process, the microprocessor giant also said it has manufactured a prototype, 153-Mbit SRAM based on the technology. Measuring 119-mm2 Intel’s “shuttle test” device is a six-transistor chip that boasts a cell size of only 0.346-micron2 according to the company.
The 45-nm device includes several components on the same chip, including an SRAM array, PROM array, phase-lock-loop, I/O, register file and a discrete test structure, according to Intel.
The announcement demonstrates that Intel’s 45-nm process is on track and expected to be ready for mass production in the second half of 2007, said Mark Bohr, an Intel senior fellow and director of process architecture and integration.
Despite recent 45-nm announcements made by NEC, Toshiba and other chip makers, Intel claims to be the leader in this technology arena. “I think it’s safe to say that we’re ahead,” Bohr said. “I’ve seen the other announcements, but they don’t have the level of detail that we’re talking about.”
Bohr declined to comment on the specifics of Intel’s 45-nm process, but he disclosed that the company is still not considering the use of silicon-on-insulator (SOI) technology. For years, Intel has dismissed the need to use SOI. “This technology will continue to use strained silicon,” he said. “We’re not using SOI.”
In contrast, microprocessor rival Advanced Micro Devices Inc. recently signed a technology license for "floating-body" silicon-on-insulator (SOI) memory developed by startup company Innovative Silicon Inc. AMD (Sunnyvale, Calif.) said it is interested in the Z-RAM (zero capacitor) technology for use in its microprocessors.
The embedded memory is a good fit with AMD, which has moved all its microprocessor production over to SOI manufacturing processes.
Intel and AMD are preparing to square off again in the x86-based processor market with next-generation products, which are due out in 2006.
Intel recently outlined its strategy to fend off competitive pressures from AMD, especially at the 65-nm node. At an event, Intel reannounced its roadmap of dual-core mobile, desktop and server processors at the 65-nm node. The company also claimed that it will have no less than four wafer fabs in its arsenal that will manufacturer chips based on the 65-nm process.
Intel has also announced three 300-mm fabs capable of 45-nm chip production, including the D1D plant in Oregon, Fab 32 in Arizona and Fab 28 in Israel. In 2005, Intel has invested more than $4 billion in new fabs and upgrades.
