News & Analysis
Intel tips 45-nm process, demos chips
Mark LaPedus
1/25/2006 12:02 PM EST
Compared to its 65-nm process, Intel (Santa Clara, Calif.) claims that its new 45-nm technology has a two-fold improvement in transistor density, a 20-percent jump in switching speeds and a 30-percent reduction in power. Since late last year, Intel has been shipping microprocessors based on its 65-nm process.
Intel’s 45-nm process, dubbed P1266, is said to incorporate copper interconnects, low-k dielectrics, strained silicon and other features. The company did not disclose if it would deploy silicon dioxide or high-k dielectric films for the critical gate stack.
It plans to manufacture 45-nm devices by using 193-nm “dry” lithography scanners instead of immersion tools, as previously expected by some analysts.
With the 45-nm process, the microprocessor giant also said it has manufactured a prototype, 153-Mbit SRAM based on the technology. Measuring 119-mm2 Intel’s “shuttle test” device is a six-transistor chip that boasts a cell size of only 0.346-micron2 according to the company.
The 45-nm device includes several components on the same chip, including an SRAM array, PROM array, phase-lock-loop, I/O, register file and a discrete test structure, according to Intel.
The announcement demonstrates that Intel’s 45-nm process is on track and expected to be ready for mass production in the second half of 2007, said Mark Bohr, an Intel senior fellow and director of process architecture and integration.



